Altera RapidIO MegaCore Function Manual do Utilizador Página 19
- Página / 198
- Índice
- MARCADORES
Avaliado. / 5. Com base em avaliações de clientes
Chapter 1: About This MegaCore Function 1–11
Release Information
August 2014 Altera Corporation RapidIO MegaCore Function
User Guide
Table 1–8 shows the recommended device speed grades for earlier device families that
the RapidIO IP core supports.
Release Information
Table 1–9 provides information about this release of the RapidIO IP core.
Altera verifies that the current version of the Quartus II software compiles the
previous version of each IP core. Any exceptions to this verification are reported in the
MegaCore IP Library Release Notes or in the errata for the RapidIO IP core in the
Knowledge Base. Altera does not verify compilation with IP core versions older than
the previous release.
Table 1–8. Recommended Device Family Speed Grades for Legacy Devices
(1)
Device
Family
Mode 1x 4x
Rate
1.25
Gbaud
2.5
Gbaud
3.125
Gbaud
5.0
Gbaud
1.25
Gbaud
2.5
Gbaud
3.125
Gbaud
5.0
Gbaud
f
MAX
31.25
MHz
62.50
MHz
78.125
MHz
125
MHz
62.5
MHz
125
MHz
156.25
MHz
250
MHz
Arria II GX -4, -5, -6 -4, -5, -6 -4, -5, -6
(2)
-4, -5, -6 -4, -5 -4, -5
(2)
Arria II GZ -3, -4 -3, -4 -3, -4 -3 -3, -4 -3, -4 -3, -4
(2)
Stratix IV -2, -3, -4 -2, -3, -4 -2, -3, -4 -2, -3, -4 -2, -3, -4 -2, -3, -4 -2, -3, -4 -2, -3
(3)
Cyclone IV GX
(4)
-6, -7, -8 -6, -7, -8 -6, -7
(2)
-6, -7, -8 -6
(5) (2) (2)
Notes to Table 1–8:
(1) In this table, the entry -n indicates that both the industrial speed grade In and the commercial speed grade Cn are supported for this device
family, RapidIO mode, and baud rate.
(2) Not supported for this device family.
(3) Altera recommends that for designs that include a 4× 5.0 Gbaud RapidIO IP core variation and that target a -3 speed grade Stratix IV GX device,
you use multiple seeds in the Quartus II Design Space Explorer to find the optimal Fitter settings to meet the timing constraints. Following the
Timing Advisor's recommendations, including optimizing for speed and using LogicLock regions may be necessary to meet timing, especially
for more complex variations implemented in the largest devices.
(4) The RapidIO IP core supports only the EP4CGX50, EP4CGX75, EP4CGX110, and EP4CGX150 Cyclone IV GX devices.
(5) Some simple Cyclone IV GX 4× variations, such as physical-layer-only variations, may meet timing at 2.5 Gbaud in -7 speed grade devices, after
following the Timing Advisor’s recommendations.
Table 1–9. RapidIO Release Information
Item Description
Version 14.0 14.0 Arria 10 Edition
Release Date June 2014 August 2014
Ordering Code IP-RIOPHY
Product ID 0095
Vendor ID 6AF7
- User Guide 1
- RapidIO MegaCore Function 1
- Contents 3
- Contents v 5
- Chapter 5. Signals 6
- Chapter 6. Software Interface 6
- Chapter 7. Testbenches 6
- Releases 10
- RapidIO IP Core Features 10
- Features 11
- Device Family Support 12
- Note to Table 1–2: 13
- Interoperability Testing 14
- Note to Table 1–4: 16
- Notes to Table 1–7: 18
- Notes to Table 1–8: 19
- Installation and Licensing 20
- 2. Getting Started 23
- Simulating IP Cores 26
- Calibration Clock 27
- Transceiver Settings 28
- IV GX Variations 28
- External Transceiver PLL 29
- Specifying Constraints 30
- Variations 32
- Core Instances 34
- Mode Selection 37
- Transceiver Selection 38
- Baud Rate 39
- Reference Clock Frequency 39
- Receive Buffer Size 39
- Transmit Buffer Size 39
- Enable 16-Bit Device ID Width 40
- Destination ID Checking 40
- Maintenance Logical Layer 41
- Port Write Tx Enable 42
- Port Write Rx Enable 42
- Avalon-MM Master 43
- Avalon-MM Slave 43
- Doorbell Slave 43
- Device ID 44
- Vendor ID 44
- Revision ID 44
- Processing Element Features 45
- Switch Support 45
- Enable Switch Support 46
- Number of Ports 46
- Port Number 46
- Source Operation 46
- Destination Operation 46
- 4. Functional Description 47
- Interfaces 48
- Avalon System Clock 49
- Reference Clock 50
- Other Input Clocks 51
- Clock Domains 51
- Notes to Figure 4–2: 52
- Notes to Table 4–2: 52
- Reset for RapidIO IP Cores 53
- Reset Controller 54
- Clocking and Reset Structure 55
- Physical Layer 56
- Physical Layer Architecture 57
- Receiver Transceiver 58
- CRC Checking and Removal 58
- Transmitter Transceiver 59
- Physical Layer Receive Buffer 60
- Transport Layer 65
- Receiver 66
- Transaction ID Ranges 67
- Concentrator Register Module 69
- Maintenance Module 72
- Maintenance Register 74
- Maintenance Slave Processor 74
- Maintenance Master Processor 76
- Port-Write Processor 78
- Registers Location 81
- Transactions 82
- Notes to Table 4–8: 84
- Notes to Table 4–9: 85
- Note to Figure 4–22: 91
- Notes to Table 4–11: 95
- Notes to Table 4–12: 96
- Note to Table 4–13: 96
- Notes to Table 4–14: 97
- Doorbell Module Block Diagram 99
- Preserving Transaction Order 100
- Doorbell Message Generation 101
- Doorbell Message Reception 102
- Note to Figure 4–30: 103
- 29’hb4b5959 104
- CRC field is not removed 105
- Note to Table 4–15: 105
- Logical Layer Modules 106
- Protocol Violations 108
- Fatal Errors 108
- Maintenance Avalon-MM Slave 109
- Maintenance Avalon-MM Master 110
- Port-Write Reception Module 111
- Input/Output Avalon-MM Slave 111
- Input/Output Avalon-MM Master 112
- Note to Table 5–2: 115
- 5–2 Chapter 5: Signals 116
- Physical Layer Signals 116
- Multicast Event Signals 117
- Note to Table 5–6: 118
- Notes to Table 5–7: 118
- Chapter 5: Signals 5–5 119
- 5–6 Chapter 5: Signals 120
- Notes to Table 5–8: 121
- 5–8 Chapter 5: Signals 122
- Chapter 5: Signals 5–9 123
- Register-Related Signals 124
- Avalon-MM Interface Signals 124
- Chapter 5: Signals 5–11 125
- 4x variations 126
- 2x and 4x variations 126
- Chapter 5: Signals 5–13 127
- Note to Table 5–19: 128
- Notes to Table 5–20: 129
- 5–16 Chapter 5: Signals 130
- Notes to Table 5–21: 131
- 5–18 Chapter 5: Signals 132
- 6. Software Interface 133
- Physical Layer Registers 136
- Note to Table 6–10: 141
- Note to Table 6–11: 143
- Note to Table 6–12: 143
- Note to Table 6–13: 144
- Note to Table 6–14: 144
- Note to Table 6–15: 144
- Note to Table 6–16: 145
- Note to Table 6–17: 145
- Notes to Table 6–18: 146
- Notes to Table 6–19: 147
- Note to Table 6–22: 148
- Note to Table 6–23: 148
- Note to Table 6–24: 148
- Receive Maintenance Registers 149
- Transmit Port-Write Registers 150
- Receive Port-Write Registers 151
- Note to Table 6–45: 154
- Note to Table 6–51: 156
- Doorbell Message Registers 158
- Note to Table 6–63: 160
- 7. Testbenches 163
- 7–2 Chapter 7: Testbenches 164
- Chapter 7: Testbenches 7–3 165
- 7–4 Chapter 7: Testbenches 166
- SWRITE Transactions 167
- NWRITE_R Transactions 168
- NWRITE Transactions 169
- NREAD Transactions 170
- Doorbell Transactions 170
- Chapter 7: Testbenches 7–9 171
- Port-Write Transactions 172
- Chapter 7: Testbenches 7–11 173
- 7–12 Chapter 7: Testbenches 174
- 8. Qsys Design Example 175
- Running Qsys 177
- Adding the Master I/O BFM 181
- Adding the On-Chip Memory 182
- Connecting Unconnected Clocks 183
- Connecting System Components 183
- Generating the System 185
- Simulating the System 186
- A. Initialization Sequence 187
- Additional Information 193
- Info–2 Additional Information 194
- Document Revision History 194
- Additional Information Info–3 195
- Info–4 Additional Information 196
- Note to Table: 197
- Typographic Conventions 198
- Info–6 Additional Information 198
Manuais e produtos relacionados com Instrumentos de medida Altera RapidIO MegaCore Function
Instrumentos de medida Altera SerialLite III Streaming MegaCore Function Manual do Utilizador
(68 páginas)
(68 páginas)
Instrumentos de medida Altera Signal Integrity Development Kit, Stratix V GX Edi Manual do Utilizador
(52 páginas)
(52 páginas)
© 2020, manymanuals-pt.com. Todos os direitos reservados. | 0.026 s |
Manymanuals.com
Manymanuals.de
Manymanuals.fr
Manymanuals.it
Manymanuals.pl
Manymanuals.cz
Manymanuals.es
Manymanuals-pt.com
Comentários a estes Manuais