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Chapter 6: Software Interface 6–15
Transport and Logical Layer Registers
August 2014 Altera Corporation RapidIO MegaCore Function
User Guide
Command and Status Registers (CSRs)
Table 6–20 through Table 6–25 describe the command and status registers.
ATM_TEST_SWP
[8] RO
Processing element can support an ATOMIC test-and-swap
operation
1'b0
ATM_INC
[7] RO Processing element can support an ATOMIC increment operation
1'b0
ATM_DEC
[6] RO Processing element can support an ATOMIC decrement operation
1'b0
ATM_SET
[5] RO Processing element can support an ATOMIC set operation
1'b0
ATM_CLEAR
[4] RO Processing element can support an ATOMIC clear operation
1'b0
ATM_SWAP
[3] RO Processing element can support an ATOMIC swap operation
1'b0
PORT_WRITE
[2] RO Processing element can support a port-write operation
(5)
Implementation
Defined
[1:0] RO Reserved for this implementation
2'b00
Notes to Table 6–19:
(1) If none of the Logical layers supported by the RapidIO MegaCore is selected, the corresponding bits in the Source and Destination Operations
CAR are forced to zero. These bits cannot be set to one, even if the corresponding operations are supported by user logic attached to the
Avalon-ST pass-through interface.
(2) The default value is 1'b1 if the Avalon-MM Master is selected as an Input/Output Logical layer interface in the RapidIO parameter editor. If the
Avalon-MM Master is not selected, the value is 1'b0.
(3) The default value is set in the RapidIO parameter editor.
(4) The default value is
1'b1
if Doorbell Rx enable is turned on in the RapidIO parameter editor. If Doorbell Rx enable is turned off, the value is
1'b0
.
(5) The default value element is
1'b1
if Port Write Rx enable is turned on in the RapidIO parameter editor. If Port Write Rx enable is turned off,
the value is
1'b0.
Table 6–19. Destination Operations CAR—Offset: 0x1C
(1)
(Part 2 of 2)
Field Bits Access Comment Default
Table 6–20. Processing Element Logical Layer Control CSR—Offset: 0x4C
Field Bits Access Function Default
RSRV
[31:3] RO Reserved
29'h0
EXT_ADDR_CTRL
[2:0] RO
Controls the number of address bits generated by the Processing
element as a source and processed by the Processing element as the
target of an operation.
'b100 – Processing element supports 66 bit addresses
'b010 – Processing element supports 50 bit addresses
'b001 – Processing element supports 34 bit addresses
All other encodings reserved
3'b001
Table 6–21. Local Configuration Space Base Address 0 CSR—Offset: 0x58
Field Bits Access Function Default
RSRV
[31] RO Reserved
1'b0
LCSBA
[30:15] RO Reserved for a 34-bit local physical address
16'h0
LCSBA
[14:0] RO Reserved for a 34-bit local physical address
15'h0
- User Guide 1
- RapidIO MegaCore Function 1
- Contents 3
- Contents v 5
- Chapter 5. Signals 6
- Chapter 6. Software Interface 6
- Chapter 7. Testbenches 6
- Releases 10
- RapidIO IP Core Features 10
- Features 11
- Device Family Support 12
- Note to Table 1–2: 13
- Interoperability Testing 14
- Note to Table 1–4: 16
- Notes to Table 1–7: 18
- Notes to Table 1–8: 19
- Installation and Licensing 20
- 2. Getting Started 23
- Simulating IP Cores 26
- Calibration Clock 27
- Transceiver Settings 28
- IV GX Variations 28
- External Transceiver PLL 29
- Specifying Constraints 30
- Variations 32
- Core Instances 34
- Mode Selection 37
- Transceiver Selection 38
- Baud Rate 39
- Reference Clock Frequency 39
- Receive Buffer Size 39
- Transmit Buffer Size 39
- Enable 16-Bit Device ID Width 40
- Destination ID Checking 40
- Maintenance Logical Layer 41
- Port Write Tx Enable 42
- Port Write Rx Enable 42
- Avalon-MM Master 43
- Avalon-MM Slave 43
- Doorbell Slave 43
- Device ID 44
- Vendor ID 44
- Revision ID 44
- Processing Element Features 45
- Switch Support 45
- Enable Switch Support 46
- Number of Ports 46
- Port Number 46
- Source Operation 46
- Destination Operation 46
- 4. Functional Description 47
- Interfaces 48
- Avalon System Clock 49
- Reference Clock 50
- Other Input Clocks 51
- Clock Domains 51
- Notes to Figure 4–2: 52
- Notes to Table 4–2: 52
- Reset for RapidIO IP Cores 53
- Reset Controller 54
- Clocking and Reset Structure 55
- Physical Layer 56
- Physical Layer Architecture 57
- Receiver Transceiver 58
- CRC Checking and Removal 58
- Transmitter Transceiver 59
- Physical Layer Receive Buffer 60
- Transport Layer 65
- Receiver 66
- Transaction ID Ranges 67
- Concentrator Register Module 69
- Maintenance Module 72
- Maintenance Register 74
- Maintenance Slave Processor 74
- Maintenance Master Processor 76
- Port-Write Processor 78
- Registers Location 81
- Transactions 82
- Notes to Table 4–8: 84
- Notes to Table 4–9: 85
- Note to Figure 4–22: 91
- Notes to Table 4–11: 95
- Notes to Table 4–12: 96
- Note to Table 4–13: 96
- Notes to Table 4–14: 97
- Doorbell Module Block Diagram 99
- Preserving Transaction Order 100
- Doorbell Message Generation 101
- Doorbell Message Reception 102
- Note to Figure 4–30: 103
- 29’hb4b5959 104
- CRC field is not removed 105
- Note to Table 4–15: 105
- Logical Layer Modules 106
- Protocol Violations 108
- Fatal Errors 108
- Maintenance Avalon-MM Slave 109
- Maintenance Avalon-MM Master 110
- Port-Write Reception Module 111
- Input/Output Avalon-MM Slave 111
- Input/Output Avalon-MM Master 112
- Note to Table 5–2: 115
- 5–2 Chapter 5: Signals 116
- Physical Layer Signals 116
- Multicast Event Signals 117
- Note to Table 5–6: 118
- Notes to Table 5–7: 118
- Chapter 5: Signals 5–5 119
- 5–6 Chapter 5: Signals 120
- Notes to Table 5–8: 121
- 5–8 Chapter 5: Signals 122
- Chapter 5: Signals 5–9 123
- Register-Related Signals 124
- Avalon-MM Interface Signals 124
- Chapter 5: Signals 5–11 125
- 4x variations 126
- 2x and 4x variations 126
- Chapter 5: Signals 5–13 127
- Note to Table 5–19: 128
- Notes to Table 5–20: 129
- 5–16 Chapter 5: Signals 130
- Notes to Table 5–21: 131
- 5–18 Chapter 5: Signals 132
- 6. Software Interface 133
- Physical Layer Registers 136
- Note to Table 6–10: 141
- Note to Table 6–11: 143
- Note to Table 6–12: 143
- Note to Table 6–13: 144
- Note to Table 6–14: 144
- Note to Table 6–15: 144
- Note to Table 6–16: 145
- Note to Table 6–17: 145
- Notes to Table 6–18: 146
- Notes to Table 6–19: 147
- Note to Table 6–22: 148
- Note to Table 6–23: 148
- Note to Table 6–24: 148
- Receive Maintenance Registers 149
- Transmit Port-Write Registers 150
- Receive Port-Write Registers 151
- Note to Table 6–45: 154
- Note to Table 6–51: 156
- Doorbell Message Registers 158
- Note to Table 6–63: 160
- 7. Testbenches 163
- 7–2 Chapter 7: Testbenches 164
- Chapter 7: Testbenches 7–3 165
- 7–4 Chapter 7: Testbenches 166
- SWRITE Transactions 167
- NWRITE_R Transactions 168
- NWRITE Transactions 169
- NREAD Transactions 170
- Doorbell Transactions 170
- Chapter 7: Testbenches 7–9 171
- Port-Write Transactions 172
- Chapter 7: Testbenches 7–11 173
- 7–12 Chapter 7: Testbenches 174
- 8. Qsys Design Example 175
- Running Qsys 177
- Adding the Master I/O BFM 181
- Adding the On-Chip Memory 182
- Connecting Unconnected Clocks 183
- Connecting System Components 183
- Generating the System 185
- Simulating the System 186
- A. Initialization Sequence 187
- Additional Information 193
- Info–2 Additional Information 194
- Document Revision History 194
- Additional Information Info–3 195
- Info–4 Additional Information 196
- Note to Table: 197
- Typographic Conventions 198
- Info–6 Additional Information 198
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