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Chapter 5: Signals 5–15
Transport and Logical Layer Signals
August 2014 Altera Corporation RapidIO MegaCore Function
User Guide
Table 5–20 describes the Avalon-ST pass-through receiver (Rx) signals.
f For more information about these signals, refer to the Avalon Interface Specifications.
Table 5–20. Avalon-ST Pass-Through Interface Receiver Signals
Signal Type Function
gen_rx_ready
Input
Indicates to the IP core that the user’s custom logic is ready to receive data on the
next clock cycle. Asserted by the sink to mark ready cycles, which are cycles in
which transfers can occur. If ready is asserted on cycle N, the cycle
(N+
READY_LATENCY
) is a ready cycle. The RapidIO IP core is designed for
READY_LATENCY
equal to1.
gen_rx_valid
Output
Used to qualify all the other output signals of the receive side pass-through
interface. On every rising edge of the clock where
gen_rx_valid
is high,
gen_rx_data
can be sampled.
(1)
gen_rx_startofpacket
Output Marks the active cycle containing the start of the packet.
(1)
gen_rx_endofpacket
Output Marks the active cycle containing the end of the packet.
(1)
gen_rx_data
Output
A 32-bit wide data bus for 1x mode, or a 64-bit wide data bus for 2x or 4x mode.
(1)
gen_rx_empty
Output
This bus identifies the number of empty bytes on the last data transfer of the
gen_rx_endofpacket
. For a 32-bit wide data bus, this bus is 2 bits wide. For a
64-bit wide data bus, this bus is 3 bits wide. The least significant bit is ignored
and assumed to be 0. The following values are supported:
(1)
32-bit bus:
2'b0X
none
2'b1X
[15:0]
64-bit bus:
3'b00X
none
3'b01X [15:0]
3'b10X [31:0]
3'b11X [47:0]
If the received number of bytes, including padding and CRC, is a multiple of four
(for a 32-bit wide data bus) or a multiple of eight (for a 64-bit wide data bus), the
value of
gen_rx_empty
is zero.
The value of gen_rx_empty does not tell you whether the final 16 bits of the data
transfer are padding or CRC bits; your custom logical layer application must
decode the header fields to determine how to interpret the received bits. Refer to
“CRC Checking and Removal” on page 4–12.
gen_rx_size
(2)
Output
Identifies the number of cycles the current packet transfer requires. This signal is
only valid on the start of packet cycle when
gen_rx_startofpacket
is asserted.
(1)
gen_rx_error
Output
Indicates that the corresponding data has an error. This signal is never asserted
by the RapidIO IP core.
(1)
Notes to Table 5–20:
(1)
gen_rx_valid
is used to qualify all the other output signals of the receive side Avalon-ST pass-through interface.
(2) This is not an Avalon-ST signal. The
gen_rx_size
signal is exported when the RapidIO IP core is part of a Qsys system.
- User Guide 1
- RapidIO MegaCore Function 1
- Contents 3
- Contents v 5
- Chapter 5. Signals 6
- Chapter 6. Software Interface 6
- Chapter 7. Testbenches 6
- Releases 10
- RapidIO IP Core Features 10
- Features 11
- Device Family Support 12
- Note to Table 1–2: 13
- Interoperability Testing 14
- Note to Table 1–4: 16
- Notes to Table 1–7: 18
- Notes to Table 1–8: 19
- Installation and Licensing 20
- 2. Getting Started 23
- Simulating IP Cores 26
- Calibration Clock 27
- Transceiver Settings 28
- IV GX Variations 28
- External Transceiver PLL 29
- Specifying Constraints 30
- Variations 32
- Core Instances 34
- Mode Selection 37
- Transceiver Selection 38
- Baud Rate 39
- Reference Clock Frequency 39
- Receive Buffer Size 39
- Transmit Buffer Size 39
- Enable 16-Bit Device ID Width 40
- Destination ID Checking 40
- Maintenance Logical Layer 41
- Port Write Tx Enable 42
- Port Write Rx Enable 42
- Avalon-MM Master 43
- Avalon-MM Slave 43
- Doorbell Slave 43
- Device ID 44
- Vendor ID 44
- Revision ID 44
- Processing Element Features 45
- Switch Support 45
- Enable Switch Support 46
- Number of Ports 46
- Port Number 46
- Source Operation 46
- Destination Operation 46
- 4. Functional Description 47
- Interfaces 48
- Avalon System Clock 49
- Reference Clock 50
- Other Input Clocks 51
- Clock Domains 51
- Notes to Figure 4–2: 52
- Notes to Table 4–2: 52
- Reset for RapidIO IP Cores 53
- Reset Controller 54
- Clocking and Reset Structure 55
- Physical Layer 56
- Physical Layer Architecture 57
- Receiver Transceiver 58
- CRC Checking and Removal 58
- Transmitter Transceiver 59
- Physical Layer Receive Buffer 60
- Transport Layer 65
- Receiver 66
- Transaction ID Ranges 67
- Concentrator Register Module 69
- Maintenance Module 72
- Maintenance Register 74
- Maintenance Slave Processor 74
- Maintenance Master Processor 76
- Port-Write Processor 78
- Registers Location 81
- Transactions 82
- Notes to Table 4–8: 84
- Notes to Table 4–9: 85
- Note to Figure 4–22: 91
- Notes to Table 4–11: 95
- Notes to Table 4–12: 96
- Note to Table 4–13: 96
- Notes to Table 4–14: 97
- Doorbell Module Block Diagram 99
- Preserving Transaction Order 100
- Doorbell Message Generation 101
- Doorbell Message Reception 102
- Note to Figure 4–30: 103
- 29’hb4b5959 104
- CRC field is not removed 105
- Note to Table 4–15: 105
- Logical Layer Modules 106
- Protocol Violations 108
- Fatal Errors 108
- Maintenance Avalon-MM Slave 109
- Maintenance Avalon-MM Master 110
- Port-Write Reception Module 111
- Input/Output Avalon-MM Slave 111
- Input/Output Avalon-MM Master 112
- Note to Table 5–2: 115
- 5–2 Chapter 5: Signals 116
- Physical Layer Signals 116
- Multicast Event Signals 117
- Note to Table 5–6: 118
- Notes to Table 5–7: 118
- Chapter 5: Signals 5–5 119
- 5–6 Chapter 5: Signals 120
- Notes to Table 5–8: 121
- 5–8 Chapter 5: Signals 122
- Chapter 5: Signals 5–9 123
- Register-Related Signals 124
- Avalon-MM Interface Signals 124
- Chapter 5: Signals 5–11 125
- 4x variations 126
- 2x and 4x variations 126
- Chapter 5: Signals 5–13 127
- Note to Table 5–19: 128
- Notes to Table 5–20: 129
- 5–16 Chapter 5: Signals 130
- Notes to Table 5–21: 131
- 5–18 Chapter 5: Signals 132
- 6. Software Interface 133
- Physical Layer Registers 136
- Note to Table 6–10: 141
- Note to Table 6–11: 143
- Note to Table 6–12: 143
- Note to Table 6–13: 144
- Note to Table 6–14: 144
- Note to Table 6–15: 144
- Note to Table 6–16: 145
- Note to Table 6–17: 145
- Notes to Table 6–18: 146
- Notes to Table 6–19: 147
- Note to Table 6–22: 148
- Note to Table 6–23: 148
- Note to Table 6–24: 148
- Receive Maintenance Registers 149
- Transmit Port-Write Registers 150
- Receive Port-Write Registers 151
- Note to Table 6–45: 154
- Note to Table 6–51: 156
- Doorbell Message Registers 158
- Note to Table 6–63: 160
- 7. Testbenches 163
- 7–2 Chapter 7: Testbenches 164
- Chapter 7: Testbenches 7–3 165
- 7–4 Chapter 7: Testbenches 166
- SWRITE Transactions 167
- NWRITE_R Transactions 168
- NWRITE Transactions 169
- NREAD Transactions 170
- Doorbell Transactions 170
- Chapter 7: Testbenches 7–9 171
- Port-Write Transactions 172
- Chapter 7: Testbenches 7–11 173
- 7–12 Chapter 7: Testbenches 174
- 8. Qsys Design Example 175
- Running Qsys 177
- Adding the Master I/O BFM 181
- Adding the On-Chip Memory 182
- Connecting Unconnected Clocks 183
- Connecting System Components 183
- Generating the System 185
- Simulating the System 186
- A. Initialization Sequence 187
- Additional Information 193
- Info–2 Additional Information 194
- Document Revision History 194
- Additional Information Info–3 195
- Info–4 Additional Information 196
- Note to Table: 197
- Typographic Conventions 198
- Info–6 Additional Information 198
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