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Table 6-2: ALTERA_MULT_ADD MegaFunction Output Ports
Port Name Required Description
result [] Yes Multiplier output port. Output port [WIDTH_RESULT - 1 … 0]
wide
scanouta [] No Output of scan chain A. Output port [WIDTH_A - 1..0] wide.
ALTERA_MULT_ADD Parameters
The following table lists the parameters for the ALTERA_MULT_ADD megafunction.
Table 6-3: ALTMULT_ADD Megafunction Parameters
Parameter Name Type Required Description
NUMBER_OF_MULTIPLIERS Integer Yes Number of multipliers to be added together.
Values are 1 up to 4.
WIDTH_A Integer Yes Width of the dataa[] port.
WIDTH_B Yes Width of the datab[] port.
WIDTH_RESULT Integer Yes Width of the result[] port.
INPUT_REGISTER_A[0…3] String No Specifies the clock port for the dataa[]
operand of the multiplier. Values are
UNREGISTERED, CLOCK0, CLOCK1, and
CLOCK2. If omitted, the default value is
UNREGISTERED. INPUT_REGISTER_A[1 … 3]
must have similar values with INPUT_
REGISTER_A0.
INPUT_REGISTER_B[0…3] String No Specifies the clock port for the datab[]
operand of the multiplier. Values are
UNREGISTERED, CLOCK0, CLOCK1, and
CLOCK2. If omitted, the default value is
UNREGISTERED. INPUT_REGISTER_B[1 … 3]
must have similar values with INPUT_
REGISTER_B0.
INPUT_ACLR_A[0…3] String No Specifies the asynchronous clear for the
dataa[] operand of the multiplier. Values
are NONE, ACLR0, ACLR1. If omitted, the
default value is NONE. The INPUT_ACLR_A[1
… 3] value must be set similar to the value of
INPUT_ACLR_A0.
INPUT_ACLR_B[0…3] String No Specifies the asynchronous clear for the
datab[] operand of the multiplier. Values
are NONE, ACLR0, ACLR1. If omitted, the
default value is NONE. The INPUT_ACLR_B [1
… 3] value must be set similar to the value of
INPUT_ACLR_B0.
6-12
ALTERA_MULT_ADD Parameters
UG-01063
2014.12.19
Altera Corporation
ALTERA_MULT_ADD (Multiply-Adder)
Send Feedback
- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Contents 2
- IP Cores Function Overview 6
- Design Example Files 7
- Using the Parameter Editor 9
- UG-01063 10
- 2014.12.19 10
- Legacy parameter 12
- Upgrading IP Cores 13
- Related Information 16
- Quartus II 17
- Design Flow 17
- Gate-Level Simulation 17
- RTL Simulation 17
- Simulating Altera Designs 18
- LPM_COUNTER (Counter) 19
- LPM_DIVIDE (Divider) 26
- LPM_MULT (Multiplier) 32
- LPM_MULT Ports 34
- LPM_MULT Parameters 35
- Decoder) 39
- ALTECC_ENCODER Features 40
- Ports (ALTECC_ENCODER) 45
- Ports (ALTECC_DECODER) 45
- Parameters (ALTECC_ENCODER) 46
- Parameters (ALTECC_DECODER) 46
- ALTERA_MULT_ADD 54
- ALTERA_MULT_ADD Parameters 65
- Coefficient Multiplier) 74
- ALTMULT_ACCUM 82
- ALTMULT_ACCUM Ports 85
- ALTMULT_ACCUM Parameters 87
- Altera Corporation 101
- Send Feedback 101
- ALTMULT_ADD (Multiply-Adder) 102
- ALTMULT_ADD 103
- Features 104
- Pre-adder 105
- Pre-adder Input Mode 106
- Pre-adder Square Mode 106
- Pre-adder Constant Mode 107
- Systolic Delay Register 108
- Pre-load Constant 111
- Double Accumulator 111
- Verilog HDL Prototype 112
- VHDL Component Declaration 112
- VHDL LIBRARY_USE Declaration 113
- ALTMULT_ADD Ports 113
- ALTMULT_ADD Parameters 115
- Parameter Name Type Requi 116
- Description 116
- Subscribe 138
- Complex Multiplication 139
- Canonical Representation 139
- Conventional Representation 140
- ALTMULT_COMPLEX Ports 143
- ALTMULT_COMPLEX Parameters 143
- ALTSQRT (Integer Square Root) 147
- Parameters 149
- PARALLEL_ADD (Parallel Adder) 151
- Document Revision History 156
- Date Version Changes 157
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