Altera Integer Arithmetic IP Manual do Utilizador Página 45
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data:in std_logic_vector(width_codeword-1 downto 0);
q:out std_logic_vector(width_dataword-1 downto 0));
end component;
VHDL LIBRARY_USE Declaration
The VHDL LIBRARY-USE declaration is not required if you use the VHDL Component Declaration.
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
Ports (ALTECC_ENCODER)
The following tables list the input and output ports for the ALTECC_ENCODER megafunction.
Table 5-3: ALTECC_ENCODER Megafunction Input Ports
Port Name Required Description
data[] Yes Data input port. The size of the input port depends on the WIDTH_
DATAWORD parameter value. The data[] port contains the raw data to be
encoded.
clock Yes Clock input port that provides the clock signal to synchronize the
encoding operation. The clock port is required when the LPM_
PIPELINE value is greater than 0.
clocken No Clock enable. If omitted, the default value is 1.
aclr No Asynchronous clear input. The active high aclr signal can be used at
any time to asynchronously clear the registers.
Table 5-4: ALTECC_ENCODER Megafunction Output Ports
Port Name Required Description
q[] Yes Encoded data output port. The size of the output port depends on the
WIDTH_CODEWORD parameter value.
Ports (ALTECC_DECODER)
The following tables list the input and output ports for the ALTECC_DECODER megafunction.
Table 5-5: ALTECC_DECODER Megafunction Input Ports
Port Name Required Description
data[] Yes Data input port. The size of the input port depends on the WIDTH_
CODEWORD parameter value.
UG-01063
2014.12.19
VHDL LIBRARY_USE Declaration
5-7
ALTECC (Error Correction Code: Encoder/Decoder)
Altera Corporation
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- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Contents 2
- IP Cores Function Overview 6
- Design Example Files 7
- Using the Parameter Editor 9
- UG-01063 10
- 2014.12.19 10
- Legacy parameter 12
- Upgrading IP Cores 13
- Related Information 16
- Quartus II 17
- Design Flow 17
- Gate-Level Simulation 17
- RTL Simulation 17
- Simulating Altera Designs 18
- LPM_COUNTER (Counter) 19
- LPM_DIVIDE (Divider) 26
- LPM_MULT (Multiplier) 32
- LPM_MULT Ports 34
- LPM_MULT Parameters 35
- Decoder) 39
- ALTECC_ENCODER Features 40
- Ports (ALTECC_ENCODER) 45
- Ports (ALTECC_DECODER) 45
- Parameters (ALTECC_ENCODER) 46
- Parameters (ALTECC_DECODER) 46
- ALTERA_MULT_ADD 54
- ALTERA_MULT_ADD Parameters 65
- Coefficient Multiplier) 74
- ALTMULT_ACCUM 82
- ALTMULT_ACCUM Ports 85
- ALTMULT_ACCUM Parameters 87
- Altera Corporation 101
- Send Feedback 101
- ALTMULT_ADD (Multiply-Adder) 102
- ALTMULT_ADD 103
- Features 104
- Pre-adder 105
- Pre-adder Input Mode 106
- Pre-adder Square Mode 106
- Pre-adder Constant Mode 107
- Systolic Delay Register 108
- Pre-load Constant 111
- Double Accumulator 111
- Verilog HDL Prototype 112
- VHDL Component Declaration 112
- VHDL LIBRARY_USE Declaration 113
- ALTMULT_ADD Ports 113
- ALTMULT_ADD Parameters 115
- Parameter Name Type Requi 116
- Description 116
- Subscribe 138
- Complex Multiplication 139
- Canonical Representation 139
- Conventional Representation 140
- ALTMULT_COMPLEX Ports 143
- ALTMULT_COMPLEX Parameters 143
- ALTSQRT (Integer Square Root) 147
- Parameters 149
- PARALLEL_ADD (Parallel Adder) 151
- Document Revision History 156
- Date Version Changes 157
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