Altera DQ (ALTDQ) Manual do Utilizador descarregar pdf (Página 7)

Getting Started Page 7

November 2010 Altera Corporation DQ (ALTDQ) and DQS (ALTDQS) Megafunctions

Page 4 of the ALTDQS parameter editor is the General 2 page. Table 3 on page 7

describes options available on page 4 of the ALTDQS megafunction.

Table 3. General 2 Settings (Part 1 of 2)

Option Description

Supported Devices

Cyclone II

Cyclone III, Cyclone IV GX

Stratix, Stratix GX,

Stratix II, Stratix II GX, Arria GX, HardCopy II

What is the frequency of the DQS

inputs(s)?

The input clock frequency for the

inclk

outclk

signals. For the supported frequencies, refer to the

“External Memory” chapter in the respective device

handbook.

No No Yes Yes

What is the frequency mode?

Controls internal set up of delay chains. Available

options depend upon the DQS frequency you

entered. (1)

For the respective modes, refer to the respective

device datasheet.

No No Yes Yes

What is the delay buffer mode?

Only available in custom frequency mode. Delay

buffers can be set for High or Low delay modes.

No No Yes Yes

What is the DLL delay chain

length?

Option only available in custom frequency mode. A

delay chain length of 10, 12, or 16 buffers may be

implemented.

No No Yes Yes

How much phase shifting would

you like to use for the DQS clock?

Select phase-shift with pull-down options of 0, 72, or

90°. The values calculated from previously specified

delay buffer mode and DLL delay chain setting.

No No Yes Yes

Allow DQS to be disabled during

read post-amble

Inhibits the

ddioinclk

signal during read postamble

(when DQS transitions from 0 to Z). This stops the

ddioinclk

signal from creating false clocks as the

DQS goes into a tri-state. The device architecture

cannot implement this option on the DQSn port.

Therefore, if you select this option, the DQSn port

may only be used as an output (or left used). The

ddioinclk

signal is inhibited by a register clocked

by the DLL delayed DQS.

The

dqs_areset

and

dqs_sreset

signals control

this register. You must set the

dqs_sreset

signal to

due to architectural constraints and control the

ddioinclk

signal using

dqs_areset

signal.

No No Yes Yes

1 2 3 4 5 6 7 8 9 10 11 12 ... 30 31

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