Altera DQ (ALTDQ) Manual do Utilizador descarregar pdf (Página 25)

Ports and Parameters Page 25

November 2010 Altera Corporation DQ (ALTDQ) and DQS (ALTDQS) Megafunctions

VHDL LIBRARY-USE Declaration

The VHDL LIBRARY-USE declaration is not required if you use the VHDL

component declaration.

LIBRARY altera_mf;

USE altera_mf.altera_mf_components.all;

Ports and Parameters

This section describes all of the ports and parameters that are available for the ALTDQ

and ALTDQS megafunctions.

The parameter details are only relevant if you bypass the MegaWizard

Plug-In

Manager interface and use the megafunction as a directly parameterized instantiation

in your design. The details of these parameters are hidden if you use the MegaWizard

Plug-In Manager interface.

Table 12 shows the input ports for the ALTDQ megafunction.

Table 12. ALTDQ Megafunction Input Ports

Port Name Required Description

aclr

Asynchronous clear input. If the

aclr

port is connected, the

aset

port

cannot be used.

aset

Asynchronous set input.If the

aset

port is connected, the

aclr

port

cannot be used.

datain_h[]

Yes

Data to be output to the

padio

port at the rising edge of the

outclk

signal.

The size of the port is dependent on the

NUMBER_OF_DQ

parameter.

datain_l[]

Yes

Data to be output to the

padio

port at the falling edge of the

outclk

signal. The size of the port is dependent on the

NUMBER_OF_DQ

parameter.

ddioinclk

Clock input for the negative-edge input register. If omitted, the default is

GND

. (1)

inclock

Yes Clock input that drives the data strobe.

inclocken

No Clock enable for the

inclock

port

No Output enable signal. The

port defaults to

when enabled.

outclock

Yes Clock signal for the output and

registers.

outclocken

No Clock enable signal for each clock port.

Note to Table 12:

(1) Not available for Stratix and Stratix GX devices.

1 2 ... 20 21 22 23 24 25 26 27 28 29 30 31

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