Altera Arria 10 Avalon-MM DMA Manual do Utilizador descarregar pdf (Página 57)

Table 5-18: Status and Link Training Signals

Signal Direction Description

cfg_par_err

Output Indicates that a parity error in a TLP routed to the internal

Configuration Space. This error is also logged in the Vendor

Specific Extended Capability internal error register. You must

reset the Hard IP if this error occurs.

derr_cor_ext_rcv Output Indicates a corrected error in the RX buffer. This signal is for

debug only. It is not valid until the RX buffer is filled with data.

This is a pulse, not a level, signal. Internally, the pulse is

generated with the 500 MHz clock. A pulse extender extends the

signal so that the FPGA fabric running at 250 MHz can capture

it. Because the error was corrected by the IP core, no Application

Layer intervention is required.

(3)

derr_cor_ext_rpl Output Indicates a corrected ECC error in the retry buffer. This signal is

for debug only. Because the error was corrected by the IP core,

no Application Layer intervention is required.

(3)

derr_rpl Output Indicates an uncorrectable error in the retry buffer. This signal is

for debug only.

(3)

dlup

Output When asserted, indicates that the Hard IP block is in the Data

Link Control and Management State Machine (DLCMSM) DL_

Up state.

dlup_exit

Output This signal is asserted low for one pld_clk cycle when the IP

core exits the DLCMSM DL_Up state, indicating that the Data

Link Layer has lost communication with the other end of the

PCIe link and left the Up state. When this pulse is asserted, the

Application Layer should generate an internal reset signal that is

asserted for at least 32 cycles.

ev128ns

Output Asserted every 128 ns to create a time base aligned activity.

ev1us

Output Asserted every 1µs to create a time base aligned activity.

hotrst_exit

Output Hot reset exit. This signal is asserted for 1 clock cycle when the

LTSSM exits the hot reset state. This signal should cause the

Application Layer to be reset. This signal is active low. When this

pulse is asserted, the Application Layer should generate an

internal reset signal that is asserted for at least 32 cycles.

(3)

Altera does not rigorously test or verify debug signals. Only use debug signals to observe behavior. Do

not use debug signals to drive custom logic.

5-16

Reset, Status, and Link Training Signals

UG-01145_avmm_dma

2015.05.14

Altera Corporation

IP Core Interfaces

Send Feedback

1 2 ... 52 53 54 55 56 57 58 59 60 61 62 ... 132 133

Comentários a estes Manuais

Sem comentários

Altera Arria 10 Avalon-MM DMA Manual do Utilizador Página 57

Comentários a estes Manuais

Manuais e produtos relacionados com Instrumentos de medida Altera Arria 10 Avalon-MM DMA