Altera Arria 10 Avalon-MM DMA Manual do Utilizador Página 127
- Página / 133
- Índice
- MARCADORES
Avaliado. / 5. Com base em avaliações de clientes
Additional Information
B
2015.05.14
UG-01145_avmm_dma
Subscribe
Send Feedback
Revision History for the Avalon-MM Interface with DMA
Date Version Changes Made
2015.05.14 15.0 Made the following changes to the user guide:
• Added Enable Hard IP Status Bus when using the AVMM
interface parameter in Interface System Settings on page 3-5.
This parameter is available in the IP core v15.0 and later.
2015.05.04 15.0
• Added Enable Altera Debug Master Endpoint (ADME)
parameter to support optional Native PHY register programming
with the Altera System Console.
• Added support for downstream burst read request for a payload of
size up to 4 KBytes, if Enable burst capability for RXM BAR2
port is turned on in the Parameter Editor. Previous maximum
downstream read request payload size was 512 bytes. Refer to
Arria 10 Avalon-MM DMA for PCI Express on page 9-8.
• Corrected the allowed value of the Maximum payload size
parameter for Avalon-MM DMA IP core variations, in Device
Capabilities on page 3-9.
• Corrected the supported variations to include Gen3 x2.
• Removed the High and Maximum values for the RX Buffer credit
allocation -performance for received requests parameter. These
values are no longer valid settings. Refer to System Settings on
page 3-1.
• Enhanced descriptions of channel placement, added fPLL
placement for Gen1 and Gen2 data rates, and added master CGB
location, in Physical Layout of Hard IP In Arria 10 Devices on
page 4-1.
• Reinstated Design Implementation on page 10-1 chapter.
• Added column for Avalon-ST Interface with SR-IOV variations in
Feature Comparison for all Hard IP for PCI Express IP Cores table
in Features section.
©
2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
ISO
9001:2008
Registered
www.altera.com
101 Innovation Drive, San Jose, CA 95134
- PCIe Solutions 1
- Contents 2
- Datasheet 5
- Link Width 6
- ×2 ×4 ×8 6
- Features 6
- Interface 7
- UG-01145_avmm_dma 10
- 2015.05.14 10
- Device Family Support 11
- Related Information 11
- Recommended Speed Grades 12
- Subscribe 14
- <install_dir>/ 14
- Parameter Value 16
- Directory Description 17
- Time TLP Type Payload 17
- TLP Header 17
- Creating a Quartus II Project 18
- Compiling the Design 19
- Parameter Settings 21
- Parameter Value Description 22
- Interface System Settings 25
- Error Reporting 30
- PCIe Address Space Settings 33
- IP Core Interfaces 42
- Reset & 44
- Lock Status 44
- RX Master Module 46
- TX Slave Module 48
- Signal Name Directio 49
- Description 49
- Bits Name Description 51
- Clock Signals 55
- Signal Direction Description 55
- MSI Interrupts for Endpoints 60
- Registers 70
- Altera-Defined VSEC Registers 77
- CvP Registers 78
- Bits Register Description 82
- Register Access Description 86
- Register Name 91
- Byte Offset 95
- Register Dir Description 95
- Arria 10 Reset and Clocks 100
- Clock Domains 103
- Name Frequency Clock Domain 104
- Error Handling 106
- Data Link Layer Errors 107
- Physical Layer Errors 107
- Error Type Description 107
- Transaction Layer Errors 108
- Status Bit Conditions 111
- Altera Corporation 112
- Send Feedback 112
- IP Core Architecture 113
- Hard IP for PCI Express 114
- Top-Level Interfaces 115
- Data Link Layer 116
- Physical Layer 118
- TX Packets 119
- Altera FPGA 121
- Qsys System 122
- Design Implementation 124
- SDC Timing Constraints 125
- Frequently Asked Questions 126
- Additional Information 127
- Date Version Changes Made 128
- How to Contact Altera 130
- Contact 130
- Contact Method Address 130
- Typographic Conventions 131
- Visual Cue Meaning 131
Manuais e produtos relacionados com Instrumentos de medida Altera Arria 10 Avalon-MM DMA
(32 páginas)© 2020, manymanuals-pt.com. Todos os direitos reservados. | 0.065 s |
Manymanuals.com
Manymanuals.de
Manymanuals.fr
Manymanuals.it
Manymanuals.pl
Manymanuals.cz
Manymanuals.es
Manymanuals-pt.com
Comentários a estes Manuais