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Date Version Changes Made
• Added the following optimizations for the Descriptor Controller:
• Optimized performance for smaller payloads such as 64-byte
Ethernet packets
• Reduced overhead for host updates
• Support for concurrent dynamic host updates and DMA
operation
• Support for choice to embed Descriptor Controller in the
Avalon-MM bridge or instantiate separately
• Added access to selected Configuration Space registers and link
status registers through the optional Control Register Access
(CRA) Avalon-MM slave port.
• Added simulation support for Phase 2 and Phase 3 equalization
when requested by third-party BFM for Gen3 variants.
• Added multiple MSI/MSI-X support.
Made the following changes to the user guide:
• Removed 125 MHz clock as optional refclk frequency in Arria 10
devices. Arria 10 devices support an 100 MHz reference clock as
specified by the PCI Express Base Specification, Rev 3.0
• Corrected values for Maximum payload size parameter. The sizes
available are 128 or 256 bytes.
• Enhanced definition of Device ID and Sub-system Vendor ID to
say that these registers are only valid in the Type 0 (Endpoint)
Configuration Space.
• Removed 125 MHz clock as optional refclk frequency in Arria 10
devices. Arria 10 devices support an 100 MHz reference clock as
specified by the PCI Express Base Specification, Rev 3.0.
• Added Next Steps in Creating a Design for PCI Express to
Datasheet chapter.
• Removed the Transaction Layer Protocol Details chapter. This
information only applies to the Avalon-ST interface.
• Removed txdatavalid0 signal from the PIPE interface. This
signal is not available.
• Removed references to the MegaWizard
®
Plug-In Manager. In
14.0 the IP Parameter Editor Powered by Qsys has replaced the
MegaWizard Plug-In Manager.
• Added definitions for test_in[2], test_in[6] and test_in[7].
• Corrected interface widths in the Performance and Resource
Utilization Arria 10 Avalon-MM DMA for PCI Express table in the
Datasheet: Arria 10 Avalon-MM DMA for PCIe chapter.
• Removed discussion of pclk. This clock is not customer accessible
in Arria 10 devices.
UG-01145_avmm_dma
2015.05.14
Revision History for the Avalon-MM Interface with DMA
B-3
Additional Information
Altera Corporation
Send Feedback
- PCIe Solutions 1
- Contents 2
- Datasheet 5
- Link Width 6
- ×2 ×4 ×8 6
- Features 6
- Interface 7
- UG-01145_avmm_dma 10
- 2015.05.14 10
- Device Family Support 11
- Related Information 11
- Recommended Speed Grades 12
- Subscribe 14
- <install_dir>/ 14
- Parameter Value 16
- Directory Description 17
- Time TLP Type Payload 17
- TLP Header 17
- Creating a Quartus II Project 18
- Compiling the Design 19
- Parameter Settings 21
- Parameter Value Description 22
- Interface System Settings 25
- Error Reporting 30
- PCIe Address Space Settings 33
- IP Core Interfaces 42
- Reset & 44
- Lock Status 44
- RX Master Module 46
- TX Slave Module 48
- Signal Name Directio 49
- Description 49
- Bits Name Description 51
- Clock Signals 55
- Signal Direction Description 55
- MSI Interrupts for Endpoints 60
- Registers 70
- Altera-Defined VSEC Registers 77
- CvP Registers 78
- Bits Register Description 82
- Register Access Description 86
- Register Name 91
- Byte Offset 95
- Register Dir Description 95
- Arria 10 Reset and Clocks 100
- Clock Domains 103
- Name Frequency Clock Domain 104
- Error Handling 106
- Data Link Layer Errors 107
- Physical Layer Errors 107
- Error Type Description 107
- Transaction Layer Errors 108
- Status Bit Conditions 111
- Altera Corporation 112
- Send Feedback 112
- IP Core Architecture 113
- Hard IP for PCI Express 114
- Top-Level Interfaces 115
- Data Link Layer 116
- Physical Layer 118
- TX Packets 119
- Altera FPGA 121
- Qsys System 122
- Design Implementation 124
- SDC Timing Constraints 125
- Frequently Asked Questions 126
- Additional Information 127
- Date Version Changes Made 128
- How to Contact Altera 130
- Contact 130
- Contact Method Address 130
- Typographic Conventions 131
- Visual Cue Meaning 131
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