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Table 5-2: ALTFP_ADD_SUB Resource Utilization and Performance for the Stratix Series of Devices
Device Family Precision Optimiza‐
tion
Output
latency
Adaptive
Look-Up
Tables
(ALUTs)
Dedicated
Logic
Registers
(DLRs)
Adaptive
Logic
Modules
(ALMs)
f
MAX
(MHz)
Stratix IV
single
speed
7 594 376 385 228
14 674 686 498 495
area
7 576 345 375 227
14 596 603 421 484
double
speed
7 1,198 687 824 187
14 997 1,607 1,080 398
area
7 1,106 630 762 189
14 904 1,518 1,013 265
ALTFP_ADD_SUB Design Example: Addition of Double-Precision Format
Numbers
This design example uses the ALTFP_ADD_SUB IP core to perform the addition of double-precision
format numbers using the parameter editor in the Quartus II software.
Related Information
• Floating-Point IP Cores Design Example Files on page 1-16
• Floating-Point IP Cores Design Examples
Provides the design example files for the Floating-Point IP cores
• ModelSim-Altera Software Support
Provides information about installation, usage, and troubleshooting
ALTFP_ADD_SUM Design Example: Understanding the Simulation Results
The simulation waveform in this design example is not shown in its entirety. Run the design example files
in the ModelSim-Altera software to see the complete simulation waveforms.
Figure 5-1: ALTFP_ADD_SUB Simulation Waveform
UG-01058
2014.12.19
ALTFP_ADD_SUB Design Example: Addition of Double-Precision Format Numbers
5-3
ALTFP_ADD_SUB IP Core
Altera Corporation
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- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Contents 2
- About Floating-Point IP Cores 7
- Design Flow 8
- Using the Parameter Editor 10
- File Name Description 12
- Upgrading IP Cores 15
- Related Information 18
- Floating-Point Formats 19
- Special Case Numbers 20
- Non-IEEE-754 Standard Format 21
- Integer bits 22
- Fraction bits 22
- VHDL Component Declaration 24
- VHDL LIBRARY-USE Declaration 24
- ALTERA_FP_MATRIX_INV IP Core 25
- Triangular Matrix Inversion 29
- Matrix Multiplication 29
- Matrix Inversion Operation 29
- Precision Format Numbers 30
- Sample Matrix Data 32
- Matrix Data 33
- ALTERA_FP_MATRIX_INV Signals 34
- ALTERA_FP_MATRIX_MULT IP Core 36
- . . . N-10 . . 38
- . . . N-10 38
- ALTERA_FP_MATRIX_MULT 39
- Parameter Value Description 40
- ALTERA_FP_ACC_CUSTOM IP Core 42
- ALTERA_FP_ACC_CUSTOM Signals 44
- ALTFP_ADD_SUB IP Core 48
- ALTFP_ADD_SUB Signals 51
- ALTFP_ADD_SUB 52
- ALTFP_ADD_SUB Parameters 53
- ALTFP_DIV IP Core 55
- ALTFP_DIV Truth Table 56
- ALTFP_DIV Signals 60
- ALTFP_DIV Parameters 61
- ALTFP_MULT IP Core 63
- Parameters 66
- ALTFP_MULT Signals 67
- ALTFP_SQRT 69
- ALTFP_SQRT Truth Table 70
- ALTFP_SQRT Signals 72
- ALTFP_SQRT Parameters 74
- ALTFP_EXP IP Core 75
- ALTFP_EXP Signals 78
- ALTFP_EXP 79
- ALTFP_EXP Parameters 80
- ALTFP_INV IP Core 81
- ALTFP_INV_SQRT IP Core 87
- ALTFP_INV_SQRT 90
- ALTFP_LOG 93
- ALTFP_ATAN IP Core 99
- ALTFP_ATAN Parameters 100
- Parameter 101
- Type Required Description 101
- ALTFP_SINCOS IP Core 102
- ALTFP_SINCOS Signals 103
- ALTFP_SINCOS Parameters 104
- ALTFP_ABS IP Core 105
- UG-01058 106
- 2014.12.19 106
- ALTFP_ABS Signals 107
- ALTFP_ABS 108
- ALTFP_ABS Parameters 109
- ALTFP_COMPARE IP Core 111
- Format Numbers 112
- ALTFP_COMPARE Signals 113
- ALTFP_COMPARE Parameters 114
- ALTFP_CONVERT IP Core 116
- ALTFP_CONVERT Output Latency 117
- Point Format Numbers 121
- Time Event 122
- ALTFP_CONVERT Signals 123
- ALTFP_CONVERT Parameters 125
- ALTERA_FP_FUNCTIONS IP Core 128
- Function Description 129
- ALTERA_FP_FUNCTIONS Signals 151
- Altera Corporation 152
- Send Feedback 152
- Document Revision History 156
- Date Document 157
- Changes Made 157
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