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Meaning Sign Field Exponent Field Mantissa Field
Negative Denormalized 1 All 0’s Non-zero
Positive Infinity 0 All 1’s All 0’s
Negative Infinity 1 All 1’s All 0’s
Not-a-Number (NaN) Don’t care All 1’s Non-zero
Rounding
The IEEE-754 standard defines four types of rounding modes, which are:
• round-to-nearest-even
• round-toward-zero
• round-toward-positive-infinity
• round-toward-negative-infinity
Altera floating-point IP cores support only the most commonly used rounding mode, which is the round-
to-nearest-even mode (TO_NEAREST). With round-to-nearest-even, the IP core rounds the result to the
nearest floating-point number. If the result is exactly halfway between two floating-point numbers, the IP
core rounds the result so that the LSB becomes a zero, which is even.
Non-IEEE-754 Standard Format
Only the ALTFP_CONVERT and ALTERA_FP_FUNCTIONS (when the convert function is selected)
support the fixed point format.
The fixed-point data type is similar to the conventional integer data type, except that the fixed-point data
carries a predetermined number of fractional bits. If the width of the fraction is 0, the data becomes a
normal signed integer.
The notation for fixed-point format numbers in this user guide is Qm.f, where Q designates that the
number is in Q format notation, m is the number of bits used to indicate the integer portion of the
number, and f is the number of bits used to indicate the fractional portion of the number.
For example, Q4.12 describes a number with 4 integer bits and 12 fractional bits in a 16-bit word.
The following figures show the difference between the signed-integer format and the fixed-point format
for a 32-bit number.
Figure 1-11: Signed-Integer Format
Sign
bit
Integer bits
31 0
UG-01058
2014.12.19
Rounding
1-15
About Floating-Point IP Cores
Altera Corporation
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- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Contents 2
- About Floating-Point IP Cores 7
- Design Flow 8
- Using the Parameter Editor 10
- File Name Description 12
- Upgrading IP Cores 15
- Related Information 18
- Floating-Point Formats 19
- Special Case Numbers 20
- Non-IEEE-754 Standard Format 21
- Integer bits 22
- Fraction bits 22
- VHDL Component Declaration 24
- VHDL LIBRARY-USE Declaration 24
- ALTERA_FP_MATRIX_INV IP Core 25
- Triangular Matrix Inversion 29
- Matrix Multiplication 29
- Matrix Inversion Operation 29
- Precision Format Numbers 30
- Sample Matrix Data 32
- Matrix Data 33
- ALTERA_FP_MATRIX_INV Signals 34
- ALTERA_FP_MATRIX_MULT IP Core 36
- . . . N-10 . . 38
- . . . N-10 38
- ALTERA_FP_MATRIX_MULT 39
- Parameter Value Description 40
- ALTERA_FP_ACC_CUSTOM IP Core 42
- ALTERA_FP_ACC_CUSTOM Signals 44
- ALTFP_ADD_SUB IP Core 48
- ALTFP_ADD_SUB Signals 51
- ALTFP_ADD_SUB 52
- ALTFP_ADD_SUB Parameters 53
- ALTFP_DIV IP Core 55
- ALTFP_DIV Truth Table 56
- ALTFP_DIV Signals 60
- ALTFP_DIV Parameters 61
- ALTFP_MULT IP Core 63
- Parameters 66
- ALTFP_MULT Signals 67
- ALTFP_SQRT 69
- ALTFP_SQRT Truth Table 70
- ALTFP_SQRT Signals 72
- ALTFP_SQRT Parameters 74
- ALTFP_EXP IP Core 75
- ALTFP_EXP Signals 78
- ALTFP_EXP 79
- ALTFP_EXP Parameters 80
- ALTFP_INV IP Core 81
- ALTFP_INV_SQRT IP Core 87
- ALTFP_INV_SQRT 90
- ALTFP_LOG 93
- ALTFP_ATAN IP Core 99
- ALTFP_ATAN Parameters 100
- Parameter 101
- Type Required Description 101
- ALTFP_SINCOS IP Core 102
- ALTFP_SINCOS Signals 103
- ALTFP_SINCOS Parameters 104
- ALTFP_ABS IP Core 105
- UG-01058 106
- 2014.12.19 106
- ALTFP_ABS Signals 107
- ALTFP_ABS 108
- ALTFP_ABS Parameters 109
- ALTFP_COMPARE IP Core 111
- Format Numbers 112
- ALTFP_COMPARE Signals 113
- ALTFP_COMPARE Parameters 114
- ALTFP_CONVERT IP Core 116
- ALTFP_CONVERT Output Latency 117
- Point Format Numbers 121
- Time Event 122
- ALTFP_CONVERT Signals 123
- ALTFP_CONVERT Parameters 125
- ALTERA_FP_FUNCTIONS IP Core 128
- Function Description 129
- ALTERA_FP_FUNCTIONS Signals 151
- Altera Corporation 152
- Send Feedback 152
- Document Revision History 156
- Date Document 157
- Changes Made 157
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