Altera Video and Image Processing Suite Manual do Utilizador Página 49
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Figure 2-16: Timing Diagram Showing R’G’B’ Transferred in Parallel
The figure below shows how the first few pixels of a frame are processed.
clock
din_ready
din_startofpacket
din_valid
din_data
23:16
15:8
7:0
dout_ready
dout_valid
dout_endofpacket
dout_data
23:16
15:8
7:0
1.
2.
3.
4. 5. 6. 7.
B
0,0
G
0,0
R
0,0
B
1,0
B
2,0
G
2,0
R
1,0
B
2,0
G
1,0
B
0,0
G
0,0
R
0,0
B
x,y
G
x,y
R
x,y
n.
X
X
0
din_endofpacket
dout_startofpacket
X
X
0
This example has one Avalon-ST port named din and one Avalon-ST port named dout. Data flows into
the IP core through din, is processed and flows out of the IP core through dout.
There are five signals types—ready, valid, data, startofpacket, and endofpacket—associated with each port.
The din_ready signal is an output from the IP core and indicates when the input port is ready to receive
data. The din_valid and din_data signals are both inputs. The source connected to the input port sets
din_valid to logic '1' when din_data has useful information that must be sampled. The din_startof-
packet signal is an input that is raised to indicate the start of a packet, with din_endofpacket signaling
the end of a packet. The five output port signals have equivalent but opposite semantics.
The sequence of events for this example:
1. Initially, din_ready is logic '0', indicating that the IP core is not ready to receive data on the next cycle.
Many of the Video and Image Processing Suite IP cores are not ready for a few clock cycles in between
rows of image data or in between video frames.
2. The IP core sets din_ready to logic '1', indicating that the input port is ready to receive data one clock
cycle later. The number of clock cycles of delay which must be applied to a ready signal is referred to as
2-22
Packet Transfer Examples
UG-VIPSUITE
2015.05.04
Altera Corporation
Interfaces
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- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Contents 2
- Feature Support 7
- Release Information 9
- Device Family Support 10
- IP Core Mode Latency 11
- Interfaces 28
- Video Formats 29
- D0 D1vid_data 32
- Signal Name Description 33
- Avalon-ST Video Protocol 34
- Video Data Packets 38
- Symbol transmitted first 39
- Symbol transmitted last 39
- Plane for even rows 40
- Plane for odd rows 40
- Control Data Packets 42
- Parameters 43
- Description 43
- Type Width Height Interlacin 43
- Order Symbol Order Symbol 45
- Ancillary Data Packets 46
- Packet Propagation 46
- Parameter Name Value 47
- Signal Width Direction 47
- Packet Transfer Examples 48
- Parameter Value 50
- Avalon-MM Slave Interfaces 52
- Avalon-MM Master Interfaces 55
- Related Information 56
- Getting Started 57
- OpenCore Plus IP Evaluation 59
- Control Port 60
- Format Description 61
- Interrupts 64
- Generator Lock 68
- Underflow and Overflow 70
- Timing Constraints 71
- Handling Ancillary Packets 71
- Modules Description 75
- Address Register Description 100
- UG-VIPSUITE 105
- 2015.05.04 105
- 2D FIR Filter IP Core 106
- Coefficient Precision 107
- Parameter Value Description 108
- 2D FIR Filter Signals 109
- Signal Direction Description 110
- Video Mixing IP Cores 112
- Alpha Blending 113
- Video Mixing Signals 116
- 20 Input 3 enable 121
- Chroma Resampler IP Core 122
- 4:4:4 to 4:2:2 123
- 4:2:2 to 4:4:4 123
- Vertical Resampling (4:2:0) 124
- Chroma Resampler Signals 126
- Video Clipping IP Cores 127
- Video Clipping Signals 130
- Color Plane Sequencer IP Core 135
- Rearranging Color Patterns 136
- Splitting and Duplicating 137
- Subsampled Data 138
- Color Plane Sequencer Signals 139
- IP Cores Feature 141
- Input and Output Data Types 142
- Color Space Conversion 142
- Operands 145
- Control Synchronizer IP Core 153
- Control Synchronizer Signals 157
- Deinterlacing IP Cores 160
- Deinterlacing Methods 161
- Bob with Scanline Duplication 162
- Motion-Adaptive 162
- Sobel-Based HQ Mode 164
- Frame Buffering 165
- Types Description 166
- Frame Rate Conversion 167
- Altera Corporation 168
- Send Feedback 168
- Deinterlacing Signals 176
- Register Address 190
- (Decimal) 190
- Register Suggested 190
- Settings 190
- Comments 190
- Tuning Motion Shift 191
- Frame Reader IP Core 192
- Frame Reader Signals 194
- Frame Buffer IP Cores 198
- Double Buffering 199
- Triple Buffering 199
- Locked Frame Rate Conversion 200
- Color Format 201
- Frame Buffer Signals 206
- Gamma Corrector IP Core 214
- Gamma Corrector Signals 215
- Interlacer IP Core 218
- Interlacer Parameter Settings 219
- Interlacer Signals 219
- Interlacer Control Registers 221
- Scaler II IP Core 222
- Bilinear Algorithm 223
- Double-Buffering 226
- Scaler II Parameter Settings 230
- Scaler II Signals 233
- Scaler II Control Registers 235
- Video Switching IP Cores 237
- Mixer Layer Switching 238
- Video Switching Signals 239
- Test Pattern 243
- Trace System IP Core 253
- Trace System Signals 255
- Trace Within System Console 258
- TCL Shell Commands 259
- Command Arguments Function 260
- Packet Visualization 263
- Monitor Settings 264
- Subscribe 269
- Avalon-ST Video Class Library 270
- Class Description 272
- Running the Tests 275
- Video File Reader Test 278
- Example Test Environment 281
- Video Field Life Cycle 282
- Constrained Random Test 283
- Code for Scoreboards 285
- Code for to_grey Function 286
- Complete Class Reference 287
- Method Call Description 288
- Member Description 288
- Raw Video Data Format 299
- Y 410 / A 2R 10 G 10 B 10 301
- Additional Information 306
- Date Version Changes 307
- How to Contact Altera 310
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