Altera Video and Image Processing Suite Manual do Utilizador Página 124
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Figure 7-2: 4:2:2 Data at an Edge Transition
The figure below shows 4:2:2 data at an edge transition. Without taking any account of the luma, the
interpolation to produce chroma values for sample 4 would weight samples 3 and 5 equally. From the
luma, you can see that sample 4 falls on an the low side of an edge, so sample 5 is more significant than
sample 3.
1 2
3
4
Sample No
5 6
7
+
+
+
+
+
+
+
+
= Y’
+
= Cb
+
= Cr
+
+
= CbCr
+
+
= Y’CbCr
Y’ Intensity
CbCr Color
Value
+
+
+
+
+
+
+
+
The luma-adaptive mode looks for such situations and chooses how to adjust the interpolation filter.
From phase 0, it can shift to -1/4, 0, or 1/4; from phase 1/2, it can shift to 1/4, 1/2, or 3/4. This makes the
interpolated chroma samples line up better with edges in the luma channel and is particularly noticeable
for bold synthetic edges such as text. The luma-adaptive mode does not use memory or multipliers, but
requires more logic elements than the straightforward filtered algorithm.
Vertical Resampling (4:2:0)
The Chroma Resampler IP core does not distinguish interlaced data with its vertical resampling mode. It
only supports the co-sited form of vertical resampling.
Figure 7-3: Resampling 4.4.4 to a 4.2.0 Image
The figure below shows the co-sited form of vertical resampling.
1 2
3
4
1
2
Sample No
5 6
7
8
+
+
+
+
+
+
+
+
3
4
= Y’
+
= Cb
+
= Cr
+
+
= CbCr
+
+
= Y’CbCr
+
+
+
+
+
+
+
+
For both upsampling and downsampling, the vertical resampling algorithm is fixed at nearest-neighbor.
The algorithm does not use any multipliers.
• Upsampling—uses four line buffers, each buffer being half the width of the image.
• Downsampling—uses one line buffer, which is half the width of the image.
UG-VIPSUITE
2015.05.04
Vertical Resampling (4:2:0)
7-3
Chroma Resampler IP Core
Altera Corporation
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- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Contents 2
- Feature Support 7
- Release Information 9
- Device Family Support 10
- IP Core Mode Latency 11
- Interfaces 28
- Video Formats 29
- D0 D1vid_data 32
- Signal Name Description 33
- Avalon-ST Video Protocol 34
- Video Data Packets 38
- Symbol transmitted first 39
- Symbol transmitted last 39
- Plane for even rows 40
- Plane for odd rows 40
- Control Data Packets 42
- Parameters 43
- Description 43
- Type Width Height Interlacin 43
- Order Symbol Order Symbol 45
- Ancillary Data Packets 46
- Packet Propagation 46
- Parameter Name Value 47
- Signal Width Direction 47
- Packet Transfer Examples 48
- Parameter Value 50
- Avalon-MM Slave Interfaces 52
- Avalon-MM Master Interfaces 55
- Related Information 56
- Getting Started 57
- OpenCore Plus IP Evaluation 59
- Control Port 60
- Format Description 61
- Interrupts 64
- Generator Lock 68
- Underflow and Overflow 70
- Timing Constraints 71
- Handling Ancillary Packets 71
- Modules Description 75
- Address Register Description 100
- UG-VIPSUITE 105
- 2015.05.04 105
- 2D FIR Filter IP Core 106
- Coefficient Precision 107
- Parameter Value Description 108
- 2D FIR Filter Signals 109
- Signal Direction Description 110
- Video Mixing IP Cores 112
- Alpha Blending 113
- Video Mixing Signals 116
- 20 Input 3 enable 121
- Chroma Resampler IP Core 122
- 4:4:4 to 4:2:2 123
- 4:2:2 to 4:4:4 123
- Vertical Resampling (4:2:0) 124
- Chroma Resampler Signals 126
- Video Clipping IP Cores 127
- Video Clipping Signals 130
- Color Plane Sequencer IP Core 135
- Rearranging Color Patterns 136
- Splitting and Duplicating 137
- Subsampled Data 138
- Color Plane Sequencer Signals 139
- IP Cores Feature 141
- Input and Output Data Types 142
- Color Space Conversion 142
- Operands 145
- Control Synchronizer IP Core 153
- Control Synchronizer Signals 157
- Deinterlacing IP Cores 160
- Deinterlacing Methods 161
- Bob with Scanline Duplication 162
- Motion-Adaptive 162
- Sobel-Based HQ Mode 164
- Frame Buffering 165
- Types Description 166
- Frame Rate Conversion 167
- Altera Corporation 168
- Send Feedback 168
- Deinterlacing Signals 176
- Register Address 190
- (Decimal) 190
- Register Suggested 190
- Settings 190
- Comments 190
- Tuning Motion Shift 191
- Frame Reader IP Core 192
- Frame Reader Signals 194
- Frame Buffer IP Cores 198
- Double Buffering 199
- Triple Buffering 199
- Locked Frame Rate Conversion 200
- Color Format 201
- Frame Buffer Signals 206
- Gamma Corrector IP Core 214
- Gamma Corrector Signals 215
- Interlacer IP Core 218
- Interlacer Parameter Settings 219
- Interlacer Signals 219
- Interlacer Control Registers 221
- Scaler II IP Core 222
- Bilinear Algorithm 223
- Double-Buffering 226
- Scaler II Parameter Settings 230
- Scaler II Signals 233
- Scaler II Control Registers 235
- Video Switching IP Cores 237
- Mixer Layer Switching 238
- Video Switching Signals 239
- Test Pattern 243
- Trace System IP Core 253
- Trace System Signals 255
- Trace Within System Console 258
- TCL Shell Commands 259
- Command Arguments Function 260
- Packet Visualization 263
- Monitor Settings 264
- Subscribe 269
- Avalon-ST Video Class Library 270
- Class Description 272
- Running the Tests 275
- Video File Reader Test 278
- Example Test Environment 281
- Video Field Life Cycle 282
- Constrained Random Test 283
- Code for Scoreboards 285
- Code for to_grey Function 286
- Complete Class Reference 287
- Method Call Description 288
- Member Description 288
- Raw Video Data Format 299
- Y 410 / A 2R 10 G 10 B 10 301
- Additional Information 306
- Date Version Changes 307
- How to Contact Altera 310
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