Altera Serial Digital Interface (SDI) MegaCore Function Manual do Utilizador descarregar pdf (Página 101)

Chapter 4: SDI Audio IP Cores 4–13

SDI Audio Extract MegaCore Function

February 2013 Altera Corporation Serial Digital Interface (SDI) MegaCore Function

User Guide

Table 4–13 lists the audio input and output signals for the SDI Audio Extract

MegaCore function.

Table 4–14 lists the Avalon-ST audio signals when you instantiate the SDI Audio

Extract MegaCore function in SOPC Builder.

Table 4–13. Audio Input and Output Signals

Signal Width Direction Description

aud_clk

[0:0] Input

Set this clock to 3.072 MHz that is synchronous to the

extracted audio.

For SD-SDI inputs, this mode of operation limits the core to

extracting audio that is synchronous to the video. For HD-SDI

inputs, you must generate this clock from the optional

48 kHz output or the audio must be synchronous to the

video.

aud_ws_in

[0:0] Input

Some audio receivers provide a word select output to align

the serial outputs of several audio extract cores. In these

circumstances, assert this signal to control the output timing

of the audio extract externally, otherwise set it to 0. This

signal must be a repeating cycle of high for 32

aud_clk

cycles followed by low for 32

aud_clk

cycles.

aud_de

[0:0] Output

The core asserts this data enable signal to indicate valid

information on the

aud_ws

and

aud_data

signals. In

synchronous mode, the core drives this signal high.

aud_ws

[0:0] Output

The core asserts this word select signal to provide framing

for deserialization and to indicate left or right sample of

channel pair.

aud_data

[0:0] Output

The core asserts this signal to extract the internal AES audio

signal from the AES output module. Refer to Figure 4–9.

Table 4–14. Avalon-ST Audio Signals for SDI Audio Extract MegaCore Function

Signal Width Direction Description

aud_clk

[0:0] Input

Clocked audio clock. All the audio input signals are

synchronous to this clock.

aud_ready

[0:0] Input

Avalon-ST ready signal. Assert this signal when the

device is able to receive data.

aud_valid

[0:0] Output

Avalon-ST valid signal. The MegaCore function

asserts this signal when it outputs data.

aud_sop

[0:0] Output

Avalon-ST start of packet signal. The MegaCore

function asserts this signal when a frame starts.

aud_eop

[0:0] Output

Avalon-ST end of packet signal. The MegaCore

function asserts this signal when a frame ends.

aud_channel

[7:0] Output

Avalon-ST select signal. This signal indicates which

channel is selected.

aud_data

[23:0] Output Avalon-ST data bus. This bus transfers data.

1 2 ... 96 97 98 99 100 101 102 103 104 105 106 ... 139 140

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