Altera RapidIO II MegaCore Function Manual do Utilizador descarregar pdf (Página 54)

4–12 Chapter 4: Functional Description

Logical Layer Interfaces

RapidIO II MegaCore Function August 2014 Altera Corporation

User Guide

where:

■

rio_addr[33:0]

is the 34-bit RapidIO address composed of

{xamsbs[1:0],address[28:0],3b’000}

for RapidIO header fields

xamsbs

and

address

■

mask[31:0]

is composed of {Mask register[31:4], 4b’0000}.

■

base[31:0]

is composed of {Base register[31:4], 4b’0000}.

■

xamm[1:0]

is the

XAMM

field of the

I/O Master Mapping Window

Mask

■

xamb[1:0]

is the

XAMB

field of the

I/O Master Mapping Window

Base

The RapidIO II IP core determines the Avalon-MM address from the least significant

bits of the RapidIO address and the matching window offset using the following

equation:

Avalon-MM

address[31:4]

(offset[31:4]

mask[31:4])

| (rio_addr[31:4]

~mask[31:4])

where:

■

offset[31:0]

is the offset register. The least significant four bits of this register are

always

4’b0000

■ The definitions of all other terms in the equation appear in the definition of the

matching window.

The value of the Avalon-MM

address[3:0]

is always zero, because the address is a

byte address and the I/O Logical layer master interface has a 128-bit wide datapath.

If the address does not match any window the I/O Logical layer Master module

performs the following actions:

■ Sets the Illegal Transaction Decode Error bit in the Error Management Extension

registers.

■ Sets the

ADDRESS

OUT_OF_BOUNDS

interrupt bit in the

Input/Output

Master

Interrup

t register (Table 6–54 on page 6–38).

■ Asserts the interrupt signal

io_m_mnt_irq

if this interrupt is enabled by the

corresponding bit in the

Input/Output

Master

Interrupt

Enable

(Table 6–55 on page 6–39).

■ For a received

NREAD

NWRITE_R

request packet that does not match any enabled

window, returns a RapidIO

ERROR

response packet.

User logic can clear an interrupt by writing

to the interrupt register’s corresponding

bit location.

1 2 ... 49 50 51 52 53 54 55 56 57 58 59 ... 217 218

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