Altera RapidIO II MegaCore Function Manual do Utilizador Página 160
- Página / 218
- Índice
- MARCADORES
Avaliado. / 5. Com base em avaliações de clientes
6–22 Chapter 6: Software Interface
Physical Layer Registers
RapidIO II MegaCore Function August 2014 Altera Corporation
User Guide
Receiver
Trained
[14] RO
If the lane receiver controls any transmit or receive adaptive
equalization, this bit indicates whether all of the adaptive equalizers that
this lane controls are now trained. The value of this field is the value in
the
Receiver trained
bit in the CS field the lane transmits.
1’b0: The lane receiver controls one or more adaptive equalizers and
at least one of these adaptive equalizers is not trained.
1’b1: The lane receiver controls no adaptive equalizers, or all of the
adaptive equalizers it controls are trained.
1’b0
Receiver Lane
Sync
[13] RO
Indicates the state of the lane n
lane_sync
signal.
1’b0:
lane_sync
is FALSE.
1’b1:
lane_sync
is TRUE.
1’b0
Receiver Lane
Ready
[12] RO
Indicates the state of the lane n
lane_ready
signal.
1’b0:
lane_ready
is FALSE.
1’b1:
lane_ready
is TRUE.
1’b0
8B10B_DEC_ERR
[11:8] RC
Number of 8B10B decoding errors detected on this lane since this
register bit was last read. The value saturates at 0xF (it does not roll
over). Reading the register resets this field to the value of 0.
4’h0
Lane_sync
State Change
[7] RC
Indicates the state of the
lane_sync
signal for this lane has changed
since this bit was last read. Reading the register resets this bit to the
value of 1’b0. This bit provides an indication of the burstiness of the
transmission errors that the lane receiver detected.
1’b0
Rcvr_trained
State Change
[6] RO
Indicates the state of the
rcvr_trained
signal for this lane has
changed since this bit was last read. Reading the register resets this bit
to the value of 1’b0. A change in the signal value indicates that the
training state of the adaptive equalization under the control of this
receiver has changed; frequent changes indicate a problem on the lane.
1’b0
RSRV
[5:4] RO Reserved 2’b0
Status 1 CSR
Implemented
[3] RO
Indicates whether the RapidIO implementation includes the
Lane n
Status 1 CSR
for the current lane n. The RapidIO II IP core
implements this register, so this bit always has the value of 1’b1.
1’b1
Status 2–7
CSRs
Implemented
[2:0] RO
Number of implementation-specific
Lane n Status m
CSRs for the
current lane n. The RapidIO II IP core implements the Lane n Status 2,
Lane n Status 3, and Lane n Status 4 CSRs, so this field always has the
value of 2’b011. For the value encoding, refer to RapidIO Interconnect
Specification v2.2 Part 6: LP-Serial Physical Layer Specification.
3’b011
Note to Table 6–17:
(1) Reflects the choice made in the RapidIO II parameter editor.
Table 6–17. LP-Serial Lane n Status 0—Offset: 0x210, 0x230, 0x250, 0x270 (Part 2 of 2)
Field Bits Access Function Default
- User Guide 1
- RapidIO II MegaCore Function 1
- Contents 3
- Contents v 5
- Chapter 5. Signals 6
- Chapter 6. Software Interface 6
- Chapter 7. Testbench 6
- 1. About The RapidIO II 9
- MegaCore Function 9
- Releases 10
- RapidIO II IP Core Features 10
- Features 11
- Device Family Support 12
- IP Core Verification 13
- Hardware Testing 14
- Interoperability Testing 14
- Note to Table 1–3: 16
- Notes to Table 1–4: 16
- Installation and Licensing 17
- 2. Getting Started 19
- Simulating IP Cores 22
- Transceiver Settings 26
- External Transceiver PLL 26
- 3. Parameter Settings 31
- Note to Table 3–1: 32
- Enable 16-Bit Device ID Width 33
- Logical Layer Settings 34
- Capability Registers Settings 35
- Device ID 36
- Vendor ID 36
- Revision ID 36
- Assembly ID 36
- Assembly Information CAR 37
- Enable Flow Control Support 38
- Enable Switch Support 38
- Number of Ports 38
- Port Number 39
- Maximum PDU 39
- Destination Operations CAR 40
- Port General Control CSR 40
- Port 0 Control CSR 41
- Lane n Status 0 CSR 41
- Extended Features Pointer CSR 41
- 4. Functional Description 43
- Note to Table 4–2: 44
- Clocking and Reset Structure 45
- Notes to Table 4–3: 46
- RapidIO II 47
- Transactions 55
- Notes to Table 4–6: 57
- Notes to Table 4–7: 59
- Note to Table 4–8: 59
- Note to Figure 4–9: 66
- Note to Table 4–10: 70
- Notes to Table 4–11: 71
- Table 6–60 on page 6–40 72
- Note to Table 4–12: 73
- Maintenance Module 74
- Maintenance Interface Signals 75
- Doorbell Module Block Diagram 86
- Preserving Transaction Order 87
- Doorbell Module Signals 88
- Generating a Doorbell Message 88
- Receiving a Doorbell Message 89
- Transaction ID Ranges 90
- Notes to Table 4–24: 92
- Note to Table 4–26: 94
- Note to Table 4–27: 95
- field 97
- User Receiving Write Request 100
- Logical Layer Interfaces 101
- Transport Layer 112
- Receiver 113
- Transmitter 114
- Physical Layer 115
- Physical Layer Interfaces 116
- Low-level Interface Receiver 116
- CRC Checking and Removal 117
- Protocol Violations 119
- Fatal Errors 119
- Maintenance Avalon-MM Slave 120
- Maintenance Avalon-MM Master 121
- Port-Write Reception Module 122
- Input/Output Avalon-MM Slave 122
- Input/Output Avalon-MM Master 123
- 5. Signals 125
- Physical Layer Signals 126
- Low Latency Signals 127
- Multicast Event Signals 128
- Chapter 5: Signals 5–5 129
- Note to Table 5–7: 130
- Chapter 5: Signals 5–7 131
- 5–8 Chapter 5: Signals 132
- Register-Related Signals 133
- Avalon-MM Interface Signals 133
- Note to Table 5–12: 134
- Chapter 5: Signals 5–11 135
- Note to Table 5–15: 136
- Error Reporting Signals 137
- 5–14 Chapter 5: Signals 138
- 6. Software Interface 139
- Memory Map 140
- Physical Layer Registers 144
- Note to Table 6–9: 147
- Note to Table 6–14: 154
- Note to Table 6–15: 158
- Note to Table 6–17: 160
- Note to Table 6–22: 164
- Note to Table 6–23: 164
- Note to Table 6–24: 165
- Note to Table 6–25: 165
- Note to Table 6–26: 166
- Note to Table 6–27: 167
- Notes to Table 6–28: 168
- Notes to Table 6–29: 169
- Note to Table 6–30: 169
- Note to Table 6–31: 169
- Notes to Table 6–32: 170
- Note to Table 6–34: 171
- Note to Table 6–35: 171
- Note to Table 6–36: 172
- Note to Table 6–37: 172
- Transmit Port-Write Registers 174
- Receive Port-Write Registers 175
- Note to Table 6–59: 178
- Error Management Registers 180
- Note to Table 6–66: 181
- Notes to Table 6–67: 183
- Notes to Table 6–70: 185
- Notes to Table 6–71: 185
- Doorbell Message Registers 191
- Note to Table 6–89: 193
- 7. Testbench 195
- 7–2 Chapter 7: Testbench 196
- Testbench Overview 196
- Testbench Sequence 197
- 7–4 Chapter 7: Testbench 198
- Chapter 7: Testbench 7–5 199
- SWRITE Transactions 200
- NREAD Transactions 200
- NWRITE_R Transactions 201
- NWRITE Transactions 202
- Doorbell Transactions 202
- Port-Write Transactions 203
- Testbench Completion 204
- Chapter 7: Testbench 7–11 205
- 7–12 Chapter 7: Testbench 206
- A. Initialization Sequence 207
- MegaCore Function v12.1 209
- Additional Information 213
- Info–2 Additional Information 214
- Document Revision History 214
- Additional Information Info–3 215
- Info–4 Additional Information 216
- Note to Table: 217
- Info–6 Additional Information 218
- Typographic Conventions 218
Manuais e produtos relacionados com Instrumentos de medida Altera RapidIO II MegaCore Function
Instrumentos de medida Altera SerialLite III Streaming MegaCore Function Manual do Utilizador
(68 páginas)
(68 páginas)
Instrumentos de medida Altera Signal Integrity Development Kit, Stratix V GX Edi Manual do Utilizador
(52 páginas)
(52 páginas)
© 2020, manymanuals-pt.com. Todos os direitos reservados. | 0.581 s |
Manymanuals.com
Manymanuals.de
Manymanuals.fr
Manymanuals.it
Manymanuals.pl
Manymanuals.cz
Manymanuals.es
Manymanuals-pt.com
Comentários a estes Manuais