Altera Phase-Locked Loop Reconfiguration IP Core Manual do Utilizador descarregar pdf (Página 25)

Design Example Page 25

Phase-Locked Loop Reconfiguration (ALTPLL_RECONFIG) MegafunctionFebruary 2012 Altera Corporation

The ALTPLL megafunction allows you to generate additional configuration files

without going through a compilation stage. It allows you to generate as many

unique configuration files as you need without the difficulty of multiple

compilation flows. All you need to do is to set the intended PLL settings, enter the

file name, and click Generate A Configuration File. Use this capability with the

PLL reconfiguration of multiple .mif files via external ROMs in the

ALTPLL_RECONFIG megafunction.

7. Click Finish. The the_pll.v module is built.

8. Click OK. The MegaWizard Plug-In Manager resets to page 2a so you can create a

new custom function variation.

9. In the MegaWizard Plug-In Manager pages, select or verify the configuration

settings listed in Table 7. Click Next to advance from one page to the next.

10. Click Finish. The

pll_reconfig_circuit

module is built.

Table 7. Configuration Settings for the ALTPLL_RECONFIG Megafunction

MegaWizard

Plug-In

Manager Page

Settings Value

Megafunction Under the I/O category, select ALTPLL_RECONFIG

Which device family will you be using? Stratix III

Which type of output file do you want to

create?

Verilog

What name do you want for the output file? pll_reconfig_circuit.v

Return to this page for another create

operation

Turned off

Parameter

Settings

(General)

Currently selected device family Stratix III

Match project/default Turned on

Which scan chain type will you be using Top/Bottom

Parameter

Settings

(General)

Do you want to specify initial value of the

scan chain?

Select Yes, use this file for the content data

File name

the_pll_initial_mif.mif

Ensure that this option shows the correct path of the .mif

file before compiling the design to avoid scan chain

mismatch warnings.

Do not use pre initialized RAM - initialize

from ROM instead

Turned off

Add ports to write to the scan chain from

external ROM during run time

Turned on

EDA Generate netlist Turned off

Summary

Variation file Turned on

AHDL Include file Turned on

VHDL component declaration file Turned on

Quartus II symbol file Turned on

Instantiation template file Turned on

Verilog HDL block-box file Turned on

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