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Mentor Verification IP AE AXI4-Lite User Guide, V10.3
348
VHDL Tutorials
Verifying a Master DUT
April 2014
process_write
The process_write process works in a similar way as previously described for process_read. It
uses unique path and queue identifiers to work concurrently with other processes, as shown in
Example 11-15.
Example 11-15. process_write
-- process_write : write address phase through path 0
-- This process keep receiving write address phase and push the
-- transaction into queue through push_transaction_id API.
process
variable write_trans : integer;
begin
wait_on(AXI4_RESET_0_TO_1, index, axi4_tr_if_0(index));
wait_on(AXI4_CLOCK_POSEDGE, index, axi4_tr_if_0(index));
loop
create_slave_transaction(write_trans, index, axi4_tr_if_0(index));
get_write_addr_phase(write_trans, index, axi4_tr_if_0(index));
get_config(AXI4_CONFIG_NUM_OUTSTANDING_WR_PHASE,
tmp_config_num_outstanding_wr_phase, index,
AXI4_PATH_3, axi4_tr_if_0(index));
push_transaction_id(write_trans, AXI4_QUEUE_ID_0, index,
axi4_tr_if_0(index));
end loop;
wait;
end process;
handle_write
The handle_write process works in a similar way to that previously described for handle_read.
The main difference is that the write transaction handling gets the write data and stores it in the
slave test program Internal Memory, and adhering to the state of the WSTRB write strobes
signals. There is an additional pop_transaction_id() into a queue so that the process can send a
write response phase for the transaction, as shown in Example 11-16.
- AMBA AXI4-Lite 1
- User Guide 1
- Table of Contents 10
- List of Examples 12
- List of Figures 14
- List of Tables 15
- About This User Guide 17
- Protocol Restrictions 17
- Supported Simulators 18
- Simulator GCC Requirements 18
- Chapter 1 21
- Mentor VIP Altera Edition 21
- What Is a Transaction? 22
- AXI4-Lite Transactions 22
- Chapter 2 27
- SystemVerilog API Overview 27
- Chapter 3 39
- SystemVerilog Master BFM 39
- SystemVerilog Master API 43
- Returns 44
- Example 58
- Chapter 4 63
- SystemVerilog Slave BFM 63
- SystemVerilog Slave API 68
- Arguments config_name 69
- Chapter 5 91
- SystemVerilog Monitor API 96
- Prototype 100
- Arguments 100
- April 2014 102
- SystemVerilog Monitor BFM 105
- Helper Functions 111
- SystemVerilog Tutorials 115
- Chapter 6 115
- BFM Master Test Program 116
- Verifying a Slave DUT 117
- Verifying a Master DUT 123
- Basic Slave API Definition 124
- *_valid_delay = 4 127
- *_ready_delay = 2 127
- Advanced Slave API Definition 129
- Initial Block 131
- Chapter 7 137
- VHDL API Overview 137
- Test Program VHDL 138
- Configuration 139
- Creating Transactions 139
- Transaction Definition 140
- Executing Transactions 144
- Waiting Events 145
- Access Transaction Record 146
- Operation Mode 147
- Channel Handshake Delay 147
- Handshake Delay 148
- Transaction Done 149
- Chapter 8 151
- VHDL Master BFM 151
- Master BFM Protocol Support 152
- Master Timing and Events 152
- Master BFM Configuration 152
- Master Assertions 155
- VHDL Master API 156
- Chapter 9 213
- VHDL Slave BFM 213
- Slave BFM Configuration 214
- Slave Assertions 216
- VHDL Slave API 217
- Operational 223
- Transaction 223
- Chapter 10 279
- VHDL Monitor BFM 279
- Monitor BFM Configuration 280
- Monitor Assertions 282
- VHDL Monitor API 283
- Chapter 11 335
- VHDL Tutorials 335
- BFM Slave Test Program 341
- Chapter 12 353
- Running the Qsys Tool 356
- Running a Simulation 359
- ModelSim Simulation 360
- Editing the modelsim.ini File 363
- Questa Simulation 364
- Cadence IES Simulation 364
- Synopsys VCS Simulation 366
- Appendix A 369
- AXI4-Lite Assertions 384
- Appendix B 385
- SystemVerilog Test Programs 385
- Appendix C 397
- VHDL Test Programs 397
- End-User License Agreement 409
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