Altera LVDS SERDES Manual do Utilizador descarregar pdf (Página 9)

DescriptionTypeDirectionWidthSignal Name

Receiver parallel data output. Synchronous

to rx_coreclock in (DPA-FIFO and non-

DPA modes). In soft-CDR mode, each

channel has parallel data synchronous to its

rx_divfwdclk.

DataOutputN*Jrx_out

Bitslip rollover signal. High when the next

assertion of rx_bitslip_ctrl resets the serial

bit latency to 0.

ControlOutputNrx_bitslip_max

Core clock for RX interfaces provided by the

PLL. Not available when using an external

PLL.

ClockOutput1rx_coreclock

The per channel, divided clock with the ideal

DPA phase. The recovered slow clock for a

given channel. Applicable in soft-CDR mode

only. Because each channel may have a

different ideal sampling phase, the rx_

divfwdclks may not be edge-aligned with

each other. Each rx_divfwdclk must drive

the core logic with data from the same

channel.

ClockOutputNrx_divfwdclk

Asserted when the DPA block selects the ideal

phase. The Altera LVDS SERDES IP core

drives the rx_dpa_locked port. The DPA

logic asserts the rx_dpa_locked signal when

the signal settles on an ideal phase for that

given channel. The rx_dpa_locked port will

de-assert if the DPA moves two phases in the

same direction or if the DPA moves one

phase. The rx_dpa_locked signal will still

toggle when the rx_dpa_hold signal is

asserted, and should be ignored by user logic

when the rx_dpa_hold signal is asserted.

Applicable in DPA-FIFO and soft-CDR

modes only.

ControlOutputNrx_dpa_locked

Table 4: TX Signals

DescriptionTypeDirectionWidthSignal Name

Parallel data from the core.DataInputN*Jtx_in

LVDS serial output data.DataOutputNtx_out

External reference clock (sent off chip via the

TX data path). Source-synchronous with tx_

out.

ClockOutput1tx_outclock

Altera Corporation

Altera LVDS SERDES IP Core User Guide

Send Feedback

9

Signals

ug_altera_lvds

2014.08.18

1 2 3 4 5 6 7 8 9 10 11 12 13 14 ... 26 27

Comentários a estes Manuais

Sem comentários