Altera LVDS SERDES Manual do Utilizador descarregar pdf (Página 18)

Figure 7: 0° Edge Aligned tx_outclock x8 Serializer Waveform with Division Factor of 8

Use 180° to specify the tx_outclock phase to center aligned to the MSB of the serial data on tx_out (Figure

8).

Figure 8: 180° Center Aligned tx_outclock x8 Serializer Waveform with Division Factor of 8

Phase shift values of 0° through 315° will position the rising edge of the tx_outclock within the MSB of the

tx_out data. Phase shift values beginning with 360° will position the rising edge of the tx_outclock in serial

bits after the MSB. For example, a phase shift of 540° will position the rising edge in the center of the bit

after the MSB (Figure 9).

Figure 9: 540° Center Aligned tx_outclock x8 Serializer Waveform with Division Factor of 8

Use the Tx_outclock division factor drop-down list to set the tx_outclock frequency. Figure 10 shows a

x8 serialization factor using a 180° phase shift with a tx_outclock division factor of 2 (DDR clock and data

relationship).

Altera LVDS SERDES IP Core User Guide

Altera Corporation

Send Feedback

ug_altera_lvds

Setting the Transmitter Output Clock Parameters

2014.08.18

1 2 ... 13 14 15 16 17 18 19 20 21 22 23 ... 26 27

Sem comentários

Altera LVDS SERDES Manual do Utilizador Página 18