
Name Required Description
parallelterminationcontrol_b No Receives the current state of the pull up and pull
down Rt control buses from a termination logic
block. Input port [((WIDTH_PTC * NUMBER_OF_
CHANNELS) - 1)..0] wide. Port is applicable only
when the USE_TERMINATION_CONTROL parameter
value is TRUE.
Table 13: ALTIOBUF (As Bidirectional Buffer) Output Ports
This table lists the output ports for ALTIOBUF IP core (as bidirectional buffer)
Name Required Description
dataout[] Yes Buffer output port. Output port [NUMBER_OF_
CHANNELS - 1..0] wide. The I/O output buffer
element output.
Table 14: ALTIOBUF (As Bidirectional Buffer) Bidirectional Ports
This table lists the bidirectional ports for ALTIOBUF IP core (as bidirectional buffer)
Name Required Description
dataio[] Yes Bidirectional port that directly feeds a bidirectional
pin in the top-level design. Bidirectional port
[(NUMBER_OF_CHANNELS - 1)..0] wide.
dataio_b[] No Bidirectional DDR port that directly feeds a bidirec‐
tional pin in the top-level design. Bidirectional port
[(NUMBER_OF_CHANNELS - 1)..0] wide. The
negative signal input/output to/from the I/O buffer.
This port is used only if the use_differential_
mode_parameter is set to TRUE.
Table 15: ALTIOBUF (As Bidirectional Buffer) Parameter
This table lists the parameters for ALTIOBUF IP core (as bidirectional buffer)
Name Required Type Description
ENABLE_BUS_HOLD No String Specifies whether the bus hold circuitry is
enabled. Values are TRUE and FALSE.
When set to TRUE, bus hold circuitry is
enabled, and the previous value, instead of
high impedance, is assigned to the output
port when there is no valid input. If
omitted, the default is FALSE.
Currently, ENABLE_BUS_HOLD and USE_
DIFFERENTIAL_MODE cannot be used
simultaneously.
26
ALTIOBUF Signals and Parameters: As Bidirectional Buffer
UG-01024
2014.12.15
Altera Corporation
I/O Buffer (ALTIOBUF) IP Core User Guide
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