Altera I/O Buffer (ALTIOBUF) IP Core Manual do Utilizador descarregar pdf (Página 23)

Name Required Type Description

NUMBER_OF_CHANNELS Yes Integer Specifies the number of I/O buffers

that must be instantiated. Value must

be greater than or equal to 1. A value

of 1 indicates that the buffer is a 1-bit

port and accommodates wires. A value

greater than 1 indicates that the port

can be connected to a bus of width

NUMBER_OF_CHANNELS.

WIDTH_STC No Integer Specifies the width setting for the

series termination control bus.

WIDTH_PTC No Integer Specifies the width setting for the

parallel termination control bus.

USE_OE No String Specifies whether the oe port is used.

LEFT_SHIFT_SERIES_TERMINATION_

CONTROL

No String Values are True and False. If omitted,

the default is False. Available for all

supported devices except Cyclone

series device family.

PSEUDO_DIFFERENTIAL_MODE No String Specifies the pseudo differential mode.

Values are True and False. If omitted,

the default is False. Available only

when the USE_DIFFERENTIAL_MODE

parameter value is TRUE.

ALTIOBUF Signals and Parameters: As Bidirectional Buffer

Table 12: ALTIOBUF (As Bidirectional Buffer) Input Ports

This table lists the input ports for the ALTIOBUF IP core (as bidirectional buffer).

Name Required Description

datain[] Yes The input buffer input port. Input port [NUMBER_OF_

CHANNELS - 1..0] wide. The input signal to the I/O

output buffer element.

io_config_datain No Input port that feeds the datain port of IO_CONFIG for

user-driven dynamic delay chain. Input port used to

feed input data to the serial load shift register. The

value is a 1-bit wire shared among all I/O instances.

This port is available only if the USE_IN_DYNAMIC_

DELAY_CHAIN, USE_OUT_DYNAMIC_DELAY_CHAIN1, or

USE_OUT_DYNAMIC_DELAY_CHAIN2 parameter value is

TRUE.

UG-01024

2014.12.15

ALTIOBUF Signals and Parameters: As Bidirectional Buffer

I/O Buffer (ALTIOBUF) IP Core User Guide

Altera Corporation

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