Altera I/O Buffer (ALTIOBUF) IP Core Manual do Utilizador descarregar pdf (Página 19)

Table 9: ALTIOBUF (As Output Buffer) Input Ports

This table lists the input ports for the ALTIOBUF IP core (as output buffer).

Name Required Description

datain[] Yes The output buffer input port.

Input port [NUMBER_OF_CHANNELS - 1..0]

wide. For differential signals, this port supplies

the positive signal input. Inputs are fed to the I/

O output buffer element.

io_config_datain No Input port that feeds the datain port of IO_

CONFIG for user-driven dynamic delay chain.

Input port used to feed input data to the serial

load shift register. The value is a 1-bit wire

shared among all I/O instances.

This port is available when the USE_OUT_

DYNAMIC_DELAY_CHAIN1 or USE_OUT_DYNAMIC_

DELAY_CHAIN2 parameter value is TRUE.

io_config_clk No Input clock port that feeds the IO_CONFIG for

user-driven dynamic delay chain.

Note that the maximum frequency for this clock

is 30 MHz.

Input port used as the clock signal of shift

among all I/O instances.

This port is available when the USE_OUT_

DYNAMIC_DELAY_CHAIN1 or USE_OUT_DYNAMIC_

DELAY_CHAIN2 parameter value is TRUE.

io_config_clkena[] No Input clock-enable that feeds the ena port of IO_

CONFIG for user-driven dynamic delay chain.

Input port [NUMBER_OF_CHANNELS - 1..0]

wide. Input port used as the clock signal of shift

This port is available when the USE_OUT_

DYNAMIC_DELAY_CHAIN1 or USE_OUT_DYNAMIC_

DELAY_CHAIN2 parameter value is TRUE.

UG-01024

2014.12.15

ALTIOBUF Signals and Parameters: As Output Buffer

I/O Buffer (ALTIOBUF) IP Core User Guide

Altera Corporation

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