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Altera

offers the following device support levels for Altera IP cores:

• Preliminary support—Altera verifies the IP core with preliminary timing models for this device family.

The IP core meets all functional requirements, but might still be undergoing timing analysis for the

device family. You can use it in production designs with caution.

• Final support—Altera verifies the IP core with final timing models for this device family. The IP core

meets all functional and timing requirements for the device family. You can use it in production

designs.

Table 1-1: DSP IP Core Device Family Support

Device Family Support

Arria

II GX Final

Arria II GZ Final

Arria V Final

Arria 10 Final

Cyclone

IV Final

Cyclone V Final

MAX

10 FPGA Final

Stratix

IV GT Final

Stratix IV GX/E Final

Stratix V Final

Other device families No support

DSP IP Core Verification

Before releasing a version of an IP core, Altera runs comprehensive regression tests to verify its quality

and correctness. Altera generates custom variations of the IP core to exercise the various parameter

options and thoroughly simulates the resulting simulation models with the results verified against master

simulation models.

FFT IP Core Release Information

Table 1-2: FFT IP Core Release Information

Item Description

Version 14.1

Release Date December 2014

Ordering Code IP-FFT

Product ID 0034

UG-FFT

2014.12.15

DSP IP Core Verification

1-3

About This IP Core

Altera Corporation

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