Altera Cyclone II PowerPlay Early Power Estimator Manual do Utilizador descarregar pdf (Página 20)

3–4 Altera Corporation

PowerPlay Early Power Estimator User Guide For Cyclone II FPGAs May 2006

PowerPlay Early Power Estimator Spreadsheet Inputs

Table 3–2 describes the values that need to be entered in the Logic section

of the PowerPlay Early Power Estimator spreadsheet.

Table 3–2. Logic Section Information

Column Heading Description

Module Enter a name for the module in this column. This is an optional value.

Clock Freq Enter the clock frequency for the module in MHz. This value is limited by the

maximum frequency specification for the device family.

# of LUTs Enter the number of LUTs used in the whole design as reported in the Quartus II

software Compilation Report in the Fitter > Resource Section > Resource Usage

Summary section.

For the number of LUTs used, add the values from the following rows in the Fitter

Resource Usage Summary:

● -- 4 input functions

● -- 3 input functions

● -- 2 input functions

● -- Combinational cells for routing

# of FFs Enter the number of registers used in the whole design as reported in the Quartus II

software Compilation Report. The number of registers used in Cyclone II devices

is reported in the Total registers row in the Fitter > Resource Section > Resource

Usage Summary.

Toggle % The average percentage of logic toggling on each clock cycle. The toggle

percentage ranges from 0 to 100%. Typically, the toggle percentage is 12.5%,

which is the toggle percentage of a 16-bit counter. To ensure you do not

underestimate the toggle percentage, you can use a higher toggle percentage.

For example, a TFF with its input tied to V

has a toggle rate of 100% because its

output is changing logic states on every clock cycle. Refer to Figure 3–2 for an

example. Figure 3–3 shows an example of a 4-bit counter. The first TFF with least

significant bit (LSB) output

cout0 has a toggle rate of 100% because cout0

toggles on every clock cycle. The toggle rate for the second TFF with output

cout1

is 50% since

cout1 only toggles on every two clock cycles. Consequently, the

toggle rate for the third TFF with output

cout2 and fourth TFF with output cout3

are 25% and 12.5%, respectively. Therefore, the average toggle percentage for this

4-bit counter is (100 + 50 + 25 + 12.5)/4 = 46.875%.

Thermal Power (W),

Routing

This shows the estimated power consumed by the routing in W. This value is

calculated automatically.

Thermal Power (W), Block This shows the estimated power consumed by the logic elements (LEs) in W. This

value is calculated automatically.

Thermal Power (W), Total This shows the estimated power in W, based on the inputs you entered. It is the total

power consumed by logic and is equal to the routing power and the block power.

This value is calculated automatically.

User Comments Enter any comments. This is an optional entry.

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