Altera Arria V SoC Development Board Manual do Utilizador descarregar pdf (Página 49)

Chapter 2: Board Components 2–41

Memory

July 2014 Altera Corporation Arria V SoC Development Board

Reference Manual

DDR3A_DQS_P3

AU26

Differential 1.5-V

SSTL Class I

Data strobe P byte lane 3

DDR3A_DQS_N3

AT26

Differential 1.5-V

SSTL Class I

Data strobe N byte lane 3

DDR3A_ODT

AM31 1.5-V SSTL Class I On-die termination enable

DDR3A_RASN

AN31 1.5-V SSTL Class I Row address select

DDR3A_RESETN

AB29 1.5-V SSTL Class I Reset

DDR3A_WEN

AW33 1.5-V SSTL Class I Write enable

DDR3A_ZQ1

— 1.5-V SSTL Class I ZQ impedance calibration

DDR3 x16 (U29)

DDR3A_A0

AU29 1.5-V SSTL Class I Address bus

DDR3A_A1

AT29 1.5-V SSTL Class I Address bus

DDR3A_A2

AV30 1.5-V SSTL Class I Address bus

DDR3A_A3

AU30 1.5-V SSTL Class I Address bus

DDR3A_A4

AT30 1.5-V SSTL Class I Address bus

DDR3A_A5

AR30 1.5-V SSTL Class I Address bus

DDR3A_A6

AL30 1.5-V SSTL Class I Address bus

DDR3A_A7

AK30 1.5-V SSTL Class I Address bus

DDR3A_A8

AW31 1.5-V SSTL Class I Address bus

DDR3A_A9

AW30 1.5-V SSTL Class I Address bus

DDR3A_A10

AV31 1.5-V SSTL Class I Address bus

DDR3A_A11

AU31 1.5-V SSTL Class I Address bus

DDR3A_A12

AH30 1.5-V SSTL Class I Address bus

DDR3A_A13

AG30 1.5-V SSTL Class I Address bus

DDR3A_A14

AE29 1.5-V SSTL Class I Address bus

DDR3A_BA0

AT31 1.5-V SSTL Class I Bank address bus

DDR3A_BA1

AR31 1.5-V SSTL Class I Bank address bus

DDR3A_BA2

AP31 1.5-V SSTL Class I Bank address bus

DDR3A_CASN

AW32 1.5-V SSTL Class I Row address select

DDR3A_CKE

AP30 1.5-V SSTL Class I Column address select

DDR3A_CLK_P

AP29 1.5-V SSTL Class I Differential output clock

DDR3A_CLK_N

AN29 1.5-V SSTL Class I Differential output clock

DDR3A_CSN

AP32 1.5-V SSTL Class I Chip select

DDR3A_DM0

AF27 1.5-V SSTL Class I Write mask byte lane

DDR3A_DM1

AK25 1.5-V SSTL Class I Write mask byte lane

DDR3A_DQ0

AH25 1.5-V SSTL Class I Data bus

DDR3A_DQ1

AG25 1.5-V SSTL Class I Data bus

DDR3A_DQ2

AE26 1.5-V SSTL Class I Data bus

DDR3A_DQ3

AH26 1.5-V SSTL Class I Data bus

Table 2–27. DDR3 SDRAM Pin Assignments, Schematic Signal Names, and Functions (Part 3 of 7)

Board

Reference

Schematic

Signal Name

Arria V SoC Pin

Number

I/O Standard Description

1 2 ... 44 45 46 47 48 49 50 51 52 53 54 ... 69 70

Comentários a estes Manuais

Sem comentários

Altera Arria V SoC Development Board Manual do Utilizador Página 49

Comentários a estes Manuais

Manuais e produtos relacionados com Instrumentos de medida Altera Arria V SoC Development Board