Altera Arria V SoC Development Board Manual do Utilizador descarregar pdf (Página 17)

Chapter 2: Board Components 2–9

MAX V CPLD 5M2210 System Controller

July 2014 Altera Corporation Arria V SoC Development Board

Reference Manual

M570_PCIE_JTAG_EN

2.5-V PCI Express JTAG enable for the on-board USB-Blaster II

MAX_AS_CONF

2.5-V

Driven low to enable AS configuration from the EPCQ flash

through U13 to the FPGA

E11

MAX_CONF_DONE

2.5-V On-board USB-Blaster II configuration done LED

MAX_ERROR

2.5-V FPGA configuration error LED

MAX_FPGA_MISO

2.5-V FPGA to MAX V SPI bus data output

MAX_FPGA_MOSI

2.5-V FPGA to MAX V SPI bus data input

MAX_FPGA_SCK

2.5-V FPGA to MAX V SPI bus clock

MAX_FPGA_SSEL

2.5-V FPGA to MAX V SPI bus slave select

MAX_LOAD

2.5-V FPGA configuration active LED

MAX_QSPI_RSTN

2.5-V QSPI reset

MAX_RESETN

2.5-V MAX V reset push button

B10

MSEL0

2.5-V FPGA MSEL0 setting

MSEL1

2.5-V FPGA MSEL1 setting

C10

MSEL2

2.5-V FPGA MSEL2 setting

C12

MSEL3

2.5-V FPGA MSEL3 setting

MSEL4

2.5-V FPGA MSEL4 setting

E10

OVERTEMP

2.5-V Temperature monitor fan enable

D12

PGM_CONFIG

2.5-V Load the flash memory image identified by the PGM LEDs

B14

PGM_LED0

2.5-V Flash memory PGM select indicator 0

C13

PGM_LED1

2.5-V Flash memory PGM select indicator 1

B16

PGM_LED2

2.5-V Flash memory PGM select indicator 2

B13

PGM_SEL

2.5-V Toggles the

PGM_LED[2:0]

LED sequence

P13

RST

1.5-V Reset input

R12

SECURITY_MODE

1.5-V

DIP switch for the On-board USB-Blaster II to send FACTORY

command at power up

A10

SI570_EN

2.5-V Si570 programmable clock enable

SI571_EN

2.5-V Si571 programmable clock enable

R16

TRST

1.5-V Reset output

USB_B2_CLK

2.5-V On-board USB-Blaster II interface clock

USB_CFG0