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Address Bits Read /
Write
Feature Description
0x168 [7:5] RW ODI Pattern Counter
Threshold
The Pattern Counter Threshold specifies how
many patterns ODI will count after you start
the measurement
• 3'b000 : 256 patterns
• 3'b001 : 1024 patterns
• 3'b010 : 2048 patterns
• 3'b011 : 4096 patterns
• 3'b100 : 8192 patterns
• 3'b101 : 16384 patterns
• 3'b110 : 32768 patterns
• 3'b111 : Reserved
0x169
2 RW ODI Signal Processing
Control Mode
Set 1 to let the Avalon-MM Register control
ODI START and ODI RESET.
0x144 2 RW ODI Polarity Specifies the sign of the vertical height. When
0, the vertical height is negative. When 1, the
vertical height is positive.
Table 6-21: Horizontal and Vertical Addresses
Address Bits Read /
Write
Feature Description
0x143 [7:2] RW Vertical height Taken together, the horizontal phase and
vertical height specify the Cartesian x-y
coordinates of the sample point on the eye
diagram. You can specify 64 heights on the
vertical axis.
0x145 [6:0] RW Horizontal phase Taken together, the horizontal phase and
vertical height specify the Cartesian x-y
coordinates of the sample point on the eye
diagram. You can increment through 128
phases over 2 UI on the horizontal axis. The
following encodings are defined:
• 7'h71 : Horizontal Phase 1
• 7'h70 : Horizontal Phase 2
• 7'h73 : Horizontal Phase 3
• 7'h72 : Horizontal Phase 4
• 7'h77 : Horizontal Phase 5
• 7'h76 : Horizontal Phase 6
• 7'h75 : Horizontal Phase 7
• 7'h74 : Horizontal Phase 8
• 7'h7D : Horizontal Phase 9
• 7'h7C : Horizontal Phase 10
• 7'h7F : Horizontal Phase 11
• 7'h7E : Horizontal Phase 12
6-34
On-Die Instrumentation
UG-01143
2015.05.11
Altera Corporation
Reconfiguration Interface and Dynamic Reconfiguration
Send Feedback
- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Contents 2
- Device Transceiver Layout 9
- UG-01143 10
- 2015.05.11 10
- Transceiver Bank Architecture 22
- The GX Transceiver Channel 26
- The GT Transceiver Channel 27
- Receiver PMA 28
- DeserializerCDR 28
- Advanced Transmit (ATX) PLL 29
- Fractional PLL (fPLL) 29
- Calibration 30
- • Calibration on page 7-1 31
- • Arria 10 Device Datasheet 31
- Transceiver Design Flow 33
- Configure the PHY IP Core 35
- Generate the PHY IP Core 36
- Select the PLL IP Core 36
- Configure the PLL IP Core 38
- Generate the PLL IP Core 39
- Create Reconfiguration Logic 39
- Connect Datapath 40
- Compile the Design 40
- Verify Design Functionality 41
- Configuration 42
- Protocol Preset 42
- Transceiver Configuration 52
- PMA Parameters 54
- Parameters Value Description 58
- Enhanced PCS Parameters 60
- Standard PCS Parameters 70
- PCS Direct 77
- PMA Ports 80
- Name Direction Clock Domain 84
- Enhanced PCS Ports 85
- Name Bit Functionality 94
- Standard PCS Ports 99
- Name Direction Clock 105
- Description 105
- Related Information 105
- IP Core File Locations 106
- Interlaken 107
- Altera Corporation 108
- Send Feedback 108
- Reset Controller 118
- Design Example 121
- Parameter Value 122
- Ethernet 128
- Rate Match FIFO for GbE 134
- Parameters Value 139
- Transceivers 148
- Parameter Range 151
- Idle Deleted 155
- Before Deletion 155
- After Deletion 155
- 10GBASE-KR PHY IP Core 156
- Name Range Description 162
- Name Value Description 163
- 10GBASE-KR PHY Interfaces 164
- Avalon-MM Register Interface 170
- Creating a 10GBASE-KR Design 192
- Simulation Support 194
- Item Description 195
- Native PHY 197
- Clock and Reset Interfaces 198
- 1G/10GbE PHY Interfaces 206
- Register Definitions 214
- Bit R/W Name Description 215
- Addr Bit R/W Name Description 233
- Creating a 1G/10GbE Design 239
- Design Guidelines 240
- Channel Placement Guidelines 240
- XAUI PHY IP Core 242
- XAUI Supported Features 245
- XAUI PHY Release Information 247
- Device Family Support 248
- Parameterizing the XAUI PHY 249
- XAUI PHY Ports 251
- XAUI PHY Interfaces 251
- Soft PCS 253
- Acronyms 258
- PCI Express (PIPE) 259
- Supported PIPE Features 260
- Gen1/Gen2 Features 261
- Power States Description 262
- Gen3 Features 266
- PCIe Gen3 Capability 267
- Mode Enabled 267
- Gen1 Gen2 Gen3 267
- • PIPE Design Example 275
- Gen1 PIPE Gen2 PIPE Gen3 PIPE 277
- Native PHY IP Ports for PIPE 285
- Figure 2-92: x4 Configuration 294
- Figure 2-93: x8 Configuration 295
- TX PLL Selection for CPRI 300
- Auto-Negotiation 300
- Supported Features for CPRI 301
- Other Protocols 310
- TX Bit Slip 320
- TX Polarity Inversion 320
- RX Bit Slip 320
- RX Polarity Inversion 321
- Word Aligner Manual Mode 323
- RX Bit Reversal 328
- RX Byte Reversal 329
- Parameter Value Description 330
- 8B/10B Encoder and Decoder 333
- 8B/10B TX Disparity Control 334
- TX Bit Reversal 336
- TX Byte Reversal 336
- Arria 10 GT Channel Usage 344
- Transceiver PHY IP 345
- NativeLink Simulation Flow 354
- Define Control Signals Using 356
- Custom Simulation Flow 359
- How to Generate Scripts 361
- Simulator Simulation File Use 362
- PLLs and Clock Networks 364
- ATX PLL IP Core 369
- Parameter Range Description 370
- Parameters Range Description 378
- Instantiating CMU PLL IP Core 386
- CMU PLL IP Core 387
- Input Reference Clock Sources 390
- Receiver Input Pins 392
- Transmitter Clock Network 393
- GT Clock Lines 398
- Clock Generation Block 399
- Transmitter Standard PCS 404
- Transmitter PMA 404
- Clock Generation Block (CGB) 404
- Receiver Standard PCS 406
- Channel Bonding 407
- PMA and PCS Bonding 408
- Skew Calculations 410
- Using PLLs and Clock Networks 412
- Bonded Configurations 416
- Implementing PLL Cascading 420
- Mix and Match Example 422
- When Is Reset Required? 427
- How Do I Reset? 427
- Recommended Reset Sequence 428
- min 20 ns 429
- Status Signals 433
- Control Signals 433
- Arria 10 PMA Architecture 448
- Transmitter Buffer 449
- 85Ω, 100Ω, OFF 450
- Receiver 451
- Receiver Buffer 452
- High Data Rate Mode 454
- Receiver Equalization Modes 459
- Channel PLL 461
- CDR Lock Mode 462
- Loopback 463
- Transmitter Datapath 466
- Interlaken Frame Generator 468
- Interlaken CRC-32 Generator 468
- 0 0 066676767 469
- Pattern Generators 470
- S0 S1 S4 S5 S8 471
- PRBS Output 471
- Scrambler 472
- (tx_clkout) 474
- KR FEC Blocks 475
- Receiver Datapath 476
- Descrambler 477
- Interlaken Frame Synchronizer 477
- PRBS Error 478
- PRBS datain 478
- Interlaken CRC-32 Checker 479
- Enhanced PCS RX FIFO 479
- Case Word Input Output 482
- RX KR FEC Blocks 483
- Byte Serializer 485
- 8B/10B Encoder 487
- RX Polarity Inversion Feature 496
- Rate Match FIFO 496
- 8B/10B Decoder 497
- Byte Deserializer 499
- PIPE Interface 503
- Clock Data Recovery Control 504
- Reconfiguration 505
- Reconfiguration Features 507
- Configuration Files 510
- Bit Position Description 511
- Instance 512
- Arbitration 515
- Direct Reconfiguration Flow 517
- Maximum Pre-Emphasis Settings 518
- Address Bit Values 521
- Switching Transmitter PLL 523
- Switching Reference Clocks 524
- ATX Reference Clock Switching 525
- Ports and Parameters 528
- On-Die Instrumentation 535
- Address Bits Read / 536
- Feature Description 536
- Start Pattern Checker 543
- Embedded Debug Features 544
- Control and Status Registers 545
- PRBS Soft Accumulators 548
- ODI Acceleration Logic 549
- Unsupported Features 562
- Calibration Registers 564
- ATX PLL Calibration Registers 566
- Capability Registers 566
- Power-up Calibration 567
- User Recalibration 569
- Calibration Example 570
- Fractional PLL Recalibration 571
- CDR/CMU PLL Recalibration 571
- PMA Recalibration 571
- Check Calibration Status 574
- Analog Parameter Settings 575
- XCVR_A10_RX_LINK 578
- XCVR_A10_RX_TERM_SEL 579
- XCVR_VCCR_VCCT_VOLTAGE - RX 580
- CTLE Settings 580
- XCVR_A10_RX_ONE_STAGE_ENABLE 582
- VGA Settings 583
- XCVR_A10_RX_ADP_DFE_FXTAP 584
- XCVR_A10_TX_LINK 585
- XCVR_A10_TX_COMPENSATION_EN 586
- XCVR_VCCR_VCCT_VOLTAGE - TX 587
- XCVR_A10_TX_SLEW_RATE_CTRL 587
- Value Description 589
- Transmitter VOD Settings 593
- XCVR_A10_REFCLK_TERM_TRISTATE 594
- LVDS TRISTATE_ON/TRISTATE_OFF 595
- Assign To 595
- Reference clock pin 595
- Subscribe 596
- Chapter Document 607
- Changes Made 607
- Date Version Changes 626
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