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Table 8-13: ldh
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
A B IMM16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IMM16 0x0f
Table 8-14: ldhio
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
A B IMM16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IMM16 0x2f
Related Information
Cache and Tightly-Coupled Memory
ldhu / ldhuio
Instruction
load unsigned halfword from memory or I/O peripheral
Operation
rB ← 0x0000 : Mem16[rA + σ(IMM16)]
Assembler Syntax
ldhu rB, byte_offset(rA)
ldhuio rB, byte_offset(rA)
Example
ldhu r6, 100(r5)
Description
Computes the effective byte address specified by the sum of rA
and the instruction's signed 16-bit immediate value. Loads
register rB with the memory halfword located at the effective
byte address, zero extending the 16-bit value to 32 bits. The
effective byte address must be halfword aligned. If the byte
address is not a multiple of 2, the operation is undefined.
Usage
In processors with a data cache, this instruction may retrieve
the desired data from the cache instead of from memory. Use
the ldhuio instruction for peripheral I/O. In processors with a
data cache, ldhuio bypasses the cache and is guaranteed to
generate an Avalon-MM data transfer. In processors without a
data cache, ldhuio acts like ldhu.
For more information on data cache, refer to the Cache and
Tightly Coupled Memory chapter of the Nios II Software
Developer’s Handbook.
8-52
ldhu / ldhuio
NII51017
2015.04.02
Altera Corporation
Instruction Set Reference
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- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Contents 2
- Altera Corporation 10
- Introduction 10
- Send Feedback 10
- Related Information 11
- Standard Peripherals 12
- OpenCore Plus Evaluation 13
- Processor Architecture 16
- Processor Implementation 17
- Register File 18
- Floating-Point Instructions 20
- Operation 23
- Inference 23
- Reset and Debug Signals 25
- Exception Controller 26
- EIC Interface 26
- Memory and I/O Organization 27
- Instruction and Data Buses 29
- Memory and Peripheral Access 30
- Instruction Master Port 30
- Data Master Port 30
- Cache Memory 31
- Address Map 33
- Download and Execute Software 36
- Software Breakpoints 36
- Hardware Breakpoints 36
- Hardware Triggers 36
- Trace Capture 37
- Programming Model 40
- Memory Management 42
- Memory Protection 43
- Virtual Memory Address Space 43
- TLB Organization 44
- Field Name Description 45
- Memory Regions 47
- Registers 48
- General-Purpose Registers 49
- NII51003 51
- The status Register 52
- The estatus Register 54
- The bstatus Register 55
- The ienable Register 55
- The ipending Register 56
- The cpuid Register 56
- The exception Register 56
- The pteaddr Register 57
- The tlbacc Register 57
- The tlbmisc Register 58
- The badaddr Register 61
- The config Register 62
- The mpubase Register 63
- The mpuacc Register 64
- MASK Encoding Region Size 65
- The sstatus Register 69
- Working with the MPU 71
- MPU Initialization 72
- Debugger Access 72
- Working with ECC 73
- Instruction Cache Tag RAM 74
- Instruction Cache Data RAM 74
- Register File RAM Blocks 74
- MMU TLB RAM 74
- Exception Processing 75
- Exception Latency 78
- Reset Exceptions 78
- Break Exceptions 79
- Interrupt Exceptions 80
- Internal Interrupt Controller 82
- Trap Instruction 84
- Break Instruction 84
- Unimplemented Instruction 84
- Illegal Instruction 84
- Supervisor-Only Instruction 85
- Supervisor-Only Data Address 85
- Misaligned Data Address 85
- Division Error 86
- Fast TLB Miss 86
- Double TLB Miss 87
- TLB Permission Violation 87
- MPU Region Violation 87
- Other Exceptions 88
- Exception Processing Flow 88
- Handling Nested Exceptions 93
- Disabling Maskable Interrupts 95
- Virtual Address Aliasing 98
- Instruction Set Categories 99
- Move Instructions 100
- Comparison Instructions 101
- Shift and Rotate Instructions 101
- Program Control Instructions 102
- Other Control Instructions 103
- Custom Instructions 104
- No-Operation Instruction 104
- Document Revision History 105
- September 2004 1.1 106
- May 2004 1.0 Initial release 106
- Core Nios II Tab 107
- Core Selection 108
- Multiply and Divide Settings 109
- Reset Vector 109
- General Exception Vector 110
- Name Description 111
- Instruction Master Settings 112
- Advanced Features Tab 113
- Reset Signals 114
- Control Registers 114
- Exception Checking 115
- Shadow Register Sets 116
- HardCopy Compatible 116
- MMU and MPU Settings Tab 117
- JTAG Debug Module Tab 119
- Debug Level Settings 120
- Debug Signals 121
- Break Vector 121
- Custom Instruction Tab 122
- The Quartus II IP File 124
- Date Version Changes 126
- 2015.04.02 127
- NII51015 128
- Device Family Support 129
- Nios II/f Core 129
- Overview 130
- Arithmetic Logic Unit 130
- Instruction 131
- Result Latency 131
- Supported Instructions 131
- Memory Access 132
- Instruction Cache 133
- Tightly-Coupled Memory 135
- Memory Management Unit 135
- Memory Protection Unit 136
- Execution Pipeline 136
- Instruction Performance 137
- Exception Handling 138
- Nios II/s Core 141
- Nios II/e Core 146
- Instruction Execution Stages 147
- JTAG Debug Module 148
- Nios II Versions 150
- Version Release Date Notes 151
- Architecture Revisions 152
- Core Revisions 153
- JTAG Debug Module Revisions 157
- Application Binary Interface 160
- Memory Alignment 161
- Register Usage 161
- NII51016 162
- Frame Pointer Elimination 163
- Call Saved Registers 163
- Further Examples of Stacks 164
- Function Prologues 165
- Arguments and Return Values 166
- Return Values 167
- DWARF-2 Definition 168
- Object Files 168
- Relocation 168
- ABI for Linux Systems 171
- Relocation Operator 172
- Copy Relocation 173
- Jump Slot Relocation 173
- Thread-Local Storage 173
- Linux Function Calls 175
- Linux Process Initialization 176
- Global Offset Table 179
- Function Addresses 179
- Procedure Linkage Table 179
- Linux Conventions 181
- Instruction Set Reference 184
- Instruction Opcodes 185
- NII51017 186
- Assembler Pseudo-Instructions 187
- Assembler Macros 188
- Notation Meaning 189
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