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Blinky_state part 2
always_comb begin
next_counter = counter-1;
next_time_counter = time_counter;
next_red_led_bit = red_led_bit;
next_green_led_bit = green_led_bit;
next_state = state;
if (counter == 0) begin
next_counter <= 25000000-1;
next_time_counter <= time_counter + 1;
end
case (state)
starting: begin
if (time_counter == 2) begin
next_time_counter <= 0;
next_red_led_bit <= 1;
next_state <= turn_on_red;
end
end
turn_on_red: begin
if (time_counter == 4) begin
next_time_counter <= 0;
next_green_led_bit <= 1’b1;
next_time_counter <= 0;
next_state <= turn_on_green;
end
end
turn_on_green: begin
if (time_counter == 6) begin
next_time_counter <= 0;
next_red_led_bit <= 0;
next_green_led_bit <= 0;
next_state <= starting;
end
end
endcase
end
endmodule
EECS 452 – Fall 2014 Lecture 5 – Page 102/143 Tuesday – September 16, 2014
- EECS 452 – Lecture 5 1
- Lecture overview 2
- Free eBook 3
- Full Custom, ASIC, FPGA 4
- FPGA organization 6
- Coming down the road (at us) 8
- Cyclone II FPGA layout 10
- Cyclone II logic element 11
- Programmable interconnections 12
- Clock distribution network 13
- DE2-70 RAM 14
- (inc. parity) 15
- (not avail. true dual) 15
- Multipliers 16
- Advantages of an FPGA 17
- ASICs, FPGAs’ competition 18
- Who makes FPGAs? 19
- The Terasic/Altera DE2-70 20
- DE2-70 features 21
- The DE2-70 power on default 22
- DE2-70 reference materials 23
- Definitive resources 24
- Learning SystemVerilog 29
- Comments about standards 32
- Verilog DIY learning links 33
- Some Quartus II resources 35
- Processing a design 36
- Quartus II file extensions 37
- .qsf file comments 38
- DE2-70 .qsf file snippet 39
- DE0-Nano .qsf file snippet 40
- Selecting the I/O standard 41
- .sdc file comments 42
- From my .sdc file 43
- Dealing with a pin conflict 44
- Creating a project 45
- Specifying the FPGA (DE2-70) 46
- Almost ready to go 47
- It remains to . . 48
- Quartus II screen shot 49
- The warning windows 50
- Comments on module structure 52
- An Altera example 54
- Altera’s addsub.v example 55
- Verilog’s numbers 57
- Verilog’s base logic elements 58
- Full Adder 59
- Full Adder — Structural 60
- Verilog’s operators 61
- Verilog’s operators part 1 62
- Verilog’s operators part 2 63
- From IEEE Standard 1800-2009 64
- SystemVerilog’s data types 65
- Full adder — Behavioral 66
- Full adder test 68
- Syntax for looping statements 72
- For loop example 73
- For loop example result 74
- Lab exercise 3 75
- CODEC device used on DE2-70 77
- The WM8731, what and how 78
- DE2-70 schematic, CODEC 79
- DE2-70 CODEC pin assignments 80
- Need a fast D/A? 81
- ALTERA DE2-70 82
- Implementing a DDS sine table 83
- Recompiled and ran 86
- Using QuartusII Megafunctions 87
- Megafunctions continued 88
- Specifying a ROM 89
- More .mif information 91
- From Altera documentation 94
- Overflow lecture material 95
- The FPGA Blinky variations 96
- Blinking an LED 97
- Blinky comments 98
- Blinky using registers 99
- Blinky_D comments 100
- Blinky_state part 1 101
- Blinky_state part 2 102
- Blinky_state comments 103
- Loading Blinky into the FPGA 104
- Making Blinky the default 105
- Restoring the default default 106
- The FPGA breakout board 107
- Bit-serial data transfers 110
- Clock domain crossings 111
- CDC references 112
- Understanding clock domain 113
- Metastability cause 114
- An answer is ? 116
- The SPI protocol 118
- SPI timing example 119
- My DIY SPI timing example 120
- The I2S protocol 121
- I2S timing example 122
- The I2C protocol 123
- The I2C connection and timing 124
- The UART protocol 125
- The UART frame 126
- The FT232R UART/USB breakout 127
- Bit-serial comments 128
- Synchronizer module 129
- The Digilent PMod-DA2 module 130
- The DAC121S101 D/A 131
- How to make the D/A work 132
- Starting simple with the D/A 133
- The Digilent PMod-AD1 module 134
- The ADCS7476 A/D 135
- Comments 136
- From the Amazon web site 137
- FYI: Terasic DE0-Nano 138
- DE0–Nano features 139
- A low cost competitor 141
- Starting a personal library 143
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