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Viterbi IP Core Interfaces and Signals

The Viterbi Avalon-ST interface supports backpressure, which is a flow control mechanism, where a sink

can indicate to a source to stop sending data.

The ready latency on the Avalon-ST input interface is 1.

You may achieve a higher clock rate by driving the source ready signal source_rdy of the Viterbi high,

and not connecting the sink ready signal sink_rdy.

Avalon-ST Interfaces in DSP IP Cores

Avalon-ST interfaces define a standard, flexible, and modular protocol for data transfers from a source

interface to a sink interface.

The input interface is an Avalon-ST sink and the output interface is an Avalon-ST source. The Avalon-ST

interface supports packet transfers with packets interleaved across multiple channels.

Avalon-ST interface signals can describe traditional streaming interfaces supporting a single stream of

data without knowledge of channels or packet boundaries. Such interfaces typically contain data, ready,

and valid signals. Avalon-ST interfaces can also support more complex protocols for burst and packet

transfers with packets interleaved across multiple channels. The Avalon-ST interface inherently synchro‐

nizes multichannel designs, which allows you to achieve efficient, time-multiplexed implementations

without having to implement complex control logic.

Avalon-ST interfaces support backpressure, which is a flow control mechanism where a sink can signal to

a source to stop sending data. The sink typically uses backpressure to stop the flow of data when its FIFO

buffers are full or when it has congestion on its output.

Related Information

• Avalon Interface Specifications

Global Signals

Signal Name Description

clk The main system clock. The whole MegaCore

function operates on the rising edge of clk.

reset Reset. The entire decoder is asynchronously reset

when reset is asserted high. The reset signal resets

the entire system. You must deassert the reset signal

synchronously with respect to the rising edge of

clk.

Avalon-ST Sink Signals

3-14

Viterbi IP Core Interfaces and Signals

UG-VITERBI

2014.12.15

Altera Corporation

Viterbi IP Core Functional Description

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Altera Viterbi Compiler Manual do Utilizador Página 32