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Chapter 2: Board Components 2–53
On-Board Memory
May 2013 Altera Corporation Stratix III 3SL150 Development Board
Reference Manual
Table 2–46 lists the DDR2 SDRAM DIMM component reference and manufacturing
information.
DDR2 SDRAM Devices
The board supports two independent 8-bit DDR2 SDRAM interfaces on the horizontal
I/O banks.
The target speed on the side bank is 300-MHz DDR.
Table 2–47 lists the DDR2 device A interface signals. JEDEC bus widths are used.
Table 2–47 also shows a summary of the required number of pins to support the
largest possible DDR2 devices available in a ×8 data configuration.
Table 2–46. DDR2 SDRAM DIMM Component Reference and Manufacturing Information
Board Reference Description Manufacturer
Manufacturing
Part Number
Manufacturer
Website
J19
400 MHz DIMM for 128 M × 72
(1 GByte plus ECC)
Micron
Technology, Inc.
MT9HTF12872AY-800 www.micron.com
Table 2–47. DDR2 Device A Interface I/O (Part 1 of 2)
Board Reference Description
Schematic
Signal Name
I/O
Standard
Stratix III
Pin Number
U17 pin H8 Address bit 0
DDR2_DEVA_A0
SSTL-18 class I U22-F34
U17 pin H3 Address bit 1
DDR2_DEVA_A1
SSTL-18 class I U22-G34
U17 pin H7 Address bit 2
DDR2_DEVA_A2
SSTL-18 class I U22-G31
U17 pin J2 Address bit 3
DDR2_DEVA_A3
SSTL-18 class I U22-N24
U17 pin J8 Address bit 4
DDR2_DEVA_A4
SSTL-18 class I U22-L29
U17 pin J3 Address bit 5
DDR2_DEVA_A5
SSTL-18 class I U22-M30
U17 pin J7 Address bit 6
DDR2_DEVA_A6
SSTL-18 class I U22-L31
U17 pin K2 Address bit 7
DDR2_DEVA_A7
SSTL-18 class I U22-P25
U17 pin K8 Address bit 8
DDR2_DEVA_A8
SSTL-18 class I U22-K33
U17 pin K3 Address bit 9
DDR2_DEVA_A9
SSTL-18 class I U22-M29
U17 pin H2 Address bit 10
DDR2_DEVA_A10
SSTL-18 class I U22-J34
U17 pin K7 Address bit 11
DDR2_DEVA_A11
SSTL-18 class I U22-L32
U17 pin L2 Address bit 12
DDR2_DEVA_A12
SSTL-18 class I U22-P23
U17 pin L8 Address bit 13
DDR2_DEVA_A13
SSTL-18 class I U22-M26
U17 pin L3 Address bit 14
DDR2_DEVA_A14
SSTL-18 class I U22-N26
U17 pin G2 Bank address bit 0
DDR2_DEVA_BA0
SSTL-18 class I U22-H34
U17 pin G3 Bank address bit 1
DDR2_DEVA_BA1
SSTL-18 class I U22-K30
U17 pin G1 Bank address bit 2
DDR2_DEVA_BA2
SSTL-18 class I U22-J33
U17 pin C8 Data bit 0
DDR2_DEVA_DQ0
SSTL-18 class I U22-K27
U17 pin C2 Data bit 1
DDR2_DEVA_DQ1
SSTL-18 class I U22-J30
U17 pin D7 Data bit 2
DDR2_DEVA_DQ2
SSTL-18 class I U22-K28
U17 pin D3 Data bit 3
DDR2_DEVA_DQ3
SSTL-18 class I U22-J29
U17 pin D1 Data bit 4
DDR2_DEVA_DQ4
SSTL-18 class I U22-H32
- Reference Manual 1
- Contents 3
- Additional Information 4
- 1. Overview 5
- Board Component Blocks 6
- Chapter 1: Overview 1–3 7
- General Description 7
- Handling the Board 8
- 2. Board Components 9
- MSEL0 to GND 10
- Jumper (J13) 10
- Board Overview 11
- Featured FPGA (U22) 12
- Device Support 14
- I/O Resources 14
- MAX II CPLD 16
- FPGA Programming Over USB 25
- Notes to Table 2–7: 26
- Status Elements 27
- Board Specific LEDs 28
- Power Display 29
- JTAG Control DIP Switch 29
- Power Select Rotary Switch 31
- Clocking Circuitry 33
- Stratix III FPGA Clock Inputs 34
- General User Interfaces 36
- Note to Table 2–21: 37
- General User-Defined LEDs 38
- HSMC User-Defined LEDs 39
- User 7-Segment Display 40
- Power 7-Segment Display 41
- Character LCD 41
- Graphics LCD 43
- Radio at www.njr.co.jp 45
- Speaker Header 46
- Components and Interfaces 47
- High-Speed Mezzanine Cards 49
- On-Board Memory 56
- DDR2 SDRAM DIMM 57
- DDR2 SDRAM Devices 61
- QDRII+ SRAM 63
- Flash Memory 71
- Power Supply 75
- Power Measurement 76
- Notes to Table 2–60: 78
- Note to Table: 80
- Additional Information Info–3 81
- Typographic Conventions 81
- Info–4 Additional Information 82
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