Altera Stratix III Development Board Manual do Utilizador descarregar pdf (Página 19)

Chapter 2: Board Components 2–11

MAX II CPLD

May 2013 Altera Corporation Stratix III 3SL150 Development Board

Reference Manual

Data bus shared with flash and

SRAM bit 20

FSM_D20

1.8 V J21 U10 pin E5

Data bus shared with flash and

SRAM bit 21

FSM_D21

1.8 V C24 U10 pin F5

Data bus shared with flash and

SRAM bit 22

FSM_D22

1.8 V E25 U10 pin F6

Data bus shared with flash and

SRAM bit 23

FSM_D23

1.8 V D25 U10 pin G6

F12

Data bus shared with flash and

SRAM bit 24

FSM_D24

1.8 V D24 U10 pin B1

D16

Data bus shared with flash and

SRAM bit 25

FSM_D25

1.8 V A27 U10 pin C1

F13

Data bus shared with flash and

SRAM bit 26

FSM_D26

1.8 V A29 U10 pin C2

D15

Data bus shared with flash and

SRAM bit 27

FSM_D27

1.8 V C27 U10 pin D2

F14

Data bus shared with flash and

SRAM bit 28

FSM_D28

1.8 V C28 U10 pin E2

D14

Data bus shared with flash and

SRAM bit 29

FSM_D29

1.8 V E23 U10 pin F2

E12

Data bus shared with flash and

SRAM bit 30

FSM_D30

1.8 V D23 U10 pin F1

C15

Data bus shared with flash and

SRAM bit 31

FSM_D31

1.8 V B28 U10 pin G1

L13 Flash address valid

FLASH_ADVn

1.8 V C7 U9 pin F6

K14 Flash chip enable

FLASH_CEn

1.8 V K25 U9 pin B4

L15 Flash clock

FLASH_CLK

1.8 V K24 U9 pin E6

M16 Flash output enable

FLASH_OEn

1.8 V K23 U9 pin F8

L11 Flash ready/busy

FLASH_RDYBSYn

1.8 V L16 U9 pin F7

M15 Flash reset

FLASH_RESETn

1.8 V E13 U9 pin D4

L12 Flash write enable

FLASH_WEn

1.8 V L22 U9 pin G8

N13 Flash page select

PGM0

1.8 V — SW3 pin 1

P15 Flash page select

PGM1

1.8 V — SW3 pin 2

M14 Flash page select

PGM2

1.8 V — SW3 pin 4

N16 Flash page select

PGM3

1.8 V — SW3 pin 8

D3 FPGA configuration complete

FPGA_CONF_DONE

2.5 V AH29 —

D3 FPP configuration data bus bit 0

FPGA_DATA0

2.5 V T28 —

K4 FPP configuration data bus bit 1

FPGA_DATA1

2.5 V T27 —

M2 FPP configuration data bus bit 2

FPGA_DATA2

2.5 V R34 —

K3 FPP configuration data bus bit 3

FPGA_DATA3

2.5 V R33 —

M2 FPP configuration data bus bit 4

FPGA_DATA4

2.5 V T25 —

Table 2–5. MAX II Device Pin-out (Part 4 of 9)

MAX II

Pin Number

Description Schematic Signal Name

I/O

Standard

Stratix III

Number

Other Connections

1 2 ... 14 15 16 17 18 19 20 21 22 23 24 ... 81 82

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