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SDI Clocked Audio Output Registers

The following tables list the registers for the SDI Clocked Audio Output IP core.

Table 5-7: SDI Clocked Audio Output Register Map

NameBytes Offset

Channel 0 Register00h

Channel 1 Register01h

FIFO Status Register02h

FIFO Reset Register03h

Table 5-8: SDI Clocked Audio Output Registers

DescriptionAccessNameBit

Channel 0 Register

The user-defined channel number of audio channel 0.RWChannel 07:0

Channel 1 Register

The user-defined channel number of audio channel 1.RWChannel status RAM select7:0

FIFO Status Register

This sticky bit reports the overflow of the clocked audio

output FIFO.

ROActive channel7:0

FIFO Reset Register

Reserved for future use.WOUnused6:0

Resets the clocked audio FIFO.WOFIFO reset7

Altera Corporation

SDI Audio IP Registers

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5-9

SDI Clocked Audio Output Registers

UG-SDI-AUD

2014.06.30

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