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Port Type Required Description

usedw

(1)

wrusedw

(2)

, (4)

rdusedw

(2)

, (4)

Output No Show the number of words stored in the FIFO.

Ensure that the port width is equal to the lpm_widthu

parameter if you manually instantiate the SCFIFO IP core

or the DCFIFO IP core. For the DCFIFO_MIXED_

WIDTH IP core, the width of the wrusedw and rdusedw

ports must be equal to the LPM_WIDTHU and lpm_widthu_

r parameters respectively.

For Stratix, Stratix GX, and Cyclone devices, the FIFO IP

core shows full even before the number of words stored

reaches its maximum value. Therefore, you must always

refer to the full or wrfull port for valid write request

operation, and the empty or rdempty port for valid read

request operation regardless of the target device.

The DCFIFO IP core rdempty output may momentarily glitch when the aclr input is asserted. To

prevent an external register from capturing this glitch incorrectly, ensure that one of the following is true:

• The external register must use the same reset which is connected to the aclr input of the DCFIFO IP

core, or

• The reset connected to the aclr input of the DCFIFO IP core must be asserted synchronous to the

clock which drives the external register.

The output latency information of the FIFO IP cores is important, especially for the q output port,

because there is no output flag to indicate when the output is valid to be sampled.

SCFIFO and DCFIFO Parameters

This table lists the parameters for the SCFIFO and DCFIFO IP cores.

Parameter Type Requir

Description

lpm_width Integer Yes Specifies the width of the data and q ports for the

SCFIFO IP core and DCFIFO IP core. For the

DCFIFO_MIXED_WIDTHS IP core, this parameter

specifies only the width of the data port.

lpm_width_r Integer Yes Specifies the width of the q port for the DCFIFO_

MIXED_WIDTHS IP core.

lpm_widthu Integer Yes Specifies the width of the usedw port for the SCFIFO IP

core, or the width of the rdusedw and wrusedw ports

for the DCFIFO IP core. For the DCFIFO_MIXED_

WIDTHS IP core, it only represents the width of the

wrusedw port.

lpm_widthu_r

(4)

Integer Yes Specifies the width of the rdusedw port for the

DCFIFO_MIXED_WIDTHS IP core.

(4)

Only applicable for the DCFIFO_MIXED_WIDTHS IP core.

SCFIFO and DCFIFO Parameters

UG-MFNALT_FIFO

2014.12.17

Altera Corporation

SCFIFO and DCFIFO IP Cores User Guide

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