Altera RLDRAM II Controller MegaCore Function Manual do Utilizador Página 43
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Altera Corporation MegaCore Version 9.1 2–33
November 2009 RLDRAM II Controller MegaCore Function User Guide
Functional Description
Table 2–14 shows the variation path parameters.
Table 2–15 shows the device pin prefixes parameter.
MegaCore
Verification
MegaCore verification involves simulation testing and hardware testing.
Simulation Environment
Altera has carried out extensive functional tests using industry-standard
models to ensure the functionality of the RLDRAM II controller. In
addition, Altera has carried out a wide variety of gate-level tests on the
RLDRAM II controller to verify the post-compilation functionality of the
controller.
Hardware Testing
Table 2–16 shows the Altera development board on which Altera
hardware tested the RLDRAM II controller.
Table 2–14. Variation Path Parameters
Parameter Description
Enable hierarchy control The constraints script analyzes your design, to automatically extract the hierarchy to
your variation. To prevent the constraints script analyzing your design, turn on
Enable Hierarchy Control, and enter the correct hierarchy path to your datapath.
Hierarchy path to
RLDRAM II controller
datapath
The hierarchy path is the path to your RLDRAM II controller datapath, minus the top-
level name. The hierarchy entered in the wizard must match your design, because
the constraints scripts rely on this path for correct operation.
Table 2–15. Device Pin Prefixes
Parameter Description
Prefix all RLDRAM II pins
on the device with
This string prefixes the pin names for the FPGA pins that are connected to the
RLDRAM II controller.
Table 2–16. Altera Development Boards
Development Board Altera Device Memory Device
Stratix II Memory Demonstration Board 1 EP2S60F1020C3 Micron 18-bit CIO and SIO RLDRAM II
devices
- RLDRAM II Controller 1
- MegaCore Function User Guide 1
- UG-RLDRAM-8.1 2
- Contents 3
- Additional Information 4
- 1. About This MegaCore 5
- Function 5
- Features 6
- General 6
- Description 6
- (1) Non-DQS mode only 7
- Performance 8
- Utilization 8
- 2. Functional Description 11
- Control Logic 12
- Datapath 13
- <signal>_1 are present 14
- Memory Clock Generator 15
- Pipeline Registers 16
- DQS Group 16
- Functional Description 17
- Notes to Figure 2–4: 17
- Datapath Example 18
- Figure 2–6. Example Datapath 19
- Device-Level 22
- Configuration 22
- Example Design 24
- Interfaces 26
- Refreshes 31
- system signals 32
- Direction Description 33
- Parameters 38
- Parameter Range Description 40
- Project Settings 42
- MegaCore 43
- Verification 43
- MegaCore Verification 44
- 3. Getting Started 45
- RLDRAM II 46
- Controller 46
- Walkthrough 46
- Launch IP Toolbench 48
- Step 1: Parameterize 49
- Step 2: Constraints 51
- Step 3: Set Up Simulation 52
- Step 4: Generate 52
- Simulate the 55
- Simulate the Example Design 56
- Edit the PLL 57
- Compile the 58
- Program a 59
- Implement Your 59
- Set Up Licensing 59
- Typographic 62
- Conventions 62
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