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2–4 Chapter 2: Getting Started

MegaWizard Plug-In Manager Page Descriptions

RAM-Based Shift Register (ALTSHIFT_TAPS) Megafunction User Guide May 2013 Altera Corporation

Figure 2–4 shows an example of a shift register chain.

Create a clock enable port

Turn on this option to create an enable signal for register

ports. The register ports are always enabled if this option is

not turned on. (5)

Create an asynchronous clear port

Turn on this option to create an asynchronous clear signal.

When asserted, the outputs of the shift register are

immediately cleared.

What should the RAM block type be?

Choose the type of memory block that supports the feature,

memory configuration, and capacity for your application.

(6)

Notes for Table 2–1

(1) The widths of the

shiftin

input bus and

shiftout

output bus are identical, and they are not registered. However, the output data can be

considered synchronous with the clock because the internal read address to the memory block is synchronous to the clock.

(2) The width of the output taps is the multiplication of w (width of input data) and n (number of taps). Also, the word from the MSB of the output

taps is equivalent to the

shiftout

output bus.

(3) The combination of these groups represent the

taps[wn-1:0]

bus.

(4) The distance between taps, m, must be at least 3.

(5) The registered port is referred to as the internal register at the memory address ports. The

shiftin

and

shiftout

ports are not registered.

(6) For information about the chosen memory block type, refer to the TriMatrix Embedded Memory Block chapter of your target device handbook.

You can also choose

AUTO

if you are not particular about the RAM block type used. With the

AUTO

option, the memory block type is determined

by the Quartus II software synthesizer or Fitter at compile time. To determine the type of memory block used, check the Quartus II Fitter Report.

Table 2–1. Shift Register (RAM-based) MegaWizard Plug-in Manager [page 3] Options (Part 2 of 2)

Configuration Setting Description

Figure 2–4. Shift Register Chain Example

1 2 ... 5 6 7 8 9 10 11 12 13 14 15 ... 25 26

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