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3–30 Chapter 3: Functional Description
Interface Signals
POS-PHY Level 2 and 3 Compiler User Guide © November 2009 Altera Corporation
Preliminary
Figure 3–19 shows the timing of the Atlantic interface with a master source.
Signal Naming Convention
When you include an Atlantic interface in a design, the IP Toolbench generates the
signal names, which are prefixed by <port name>_, such as, b1_ena, b1_val,
b2_ena, b2_val.
Figure 3–18. Atlantic Interface Timing—Slave Source to Master Sink
Notes to Figure 3–18:
(1) Slave source indicates that data is available (either threshold words available, or EOP).
(2) Master sink begins reading data.
(3) Master sink decides to stop reading the data for one clock cycle. val remains asserted and data, sop, and eop hold their current
values.
(4)
Slave source indicates that it has less than threshold words available. The master sink can continue to read data until it detects val
deasserted.
(5) Master sink continues to read data, validates data with val.
(6) Slave source cannot supply any more data, so deasserts val.
(7) Master sink goes idle until dav is re-asserted.
clk
dav
ena
val
sop
eop
dat
(1) (2) (3) (4) (5) (6) (7)
Figure 3–19. Atlantic Interface Timing—Master Source to Slave Sink
Notes to Figure 3–19:
(1) Slave sink indicates it has space for at least threshold words.
(2) The master source begins writing data to the slave sink.
(3)
Slave sink indicates it has space for threshold words. Master source can continue to send data, but must ensure that the slave sink does
not overflow.
(4) Master source stops sending data
(5)
Slave sink indicates it has space for at least threshold words.
(6) Master source begins writing data to the slave sink.
(7) Slave sink indicates it still has space, but the master source has run out of data.
clk
dav
ena
sop
eop
dat
(1) (2) (3) (5)(4) (6) (7)
- User Guide 1
- UG-POSPHY2_3-9.1 2
- Contents 3
- Additional Information 4
- 1. About This Compiler 5
- Features 6
- General Description 7
- OpenCore Plus Evaluation 8
- Preliminary 10
- 2. Getting Started 13
- Launch IP Toolbench 15
- Step 1: Parameterize 17
- Step 2: Set Up Simulation 21
- Step 3: Generate 22
- Simulate the Design 24
- Testbench with NativeLink 25
- Notes to table: 26
- Compile the Design 27
- Program a Device 27
- Set Up Licensing 28
- 3. Functional Description 29
- Example Configurations 30
- Example Implementations 31
- Internal Architecture 32
- POS-PHY Interface 33
- Packet Data Width Conversion 34
- Packet FIFO Buffer 34
- ‘B’ Interface 34
- Parameters 35
- Parity Settings 36
- FIFO Buffer Settings 37
- Note to Figure 3–11: 41
- Note to Figure 3–12: 42
- FIFO Buffer Size 43
- POS-PHY Level 3 Interfaces 43
- POS-PHY Level 2 Interfaces 43
- Interface Signals 44
- Global Interface 45
- POS-PHY Level 3 Interface 45
- Notes to Table 3–9: 47
- POS-PHY Level 2 Interface 50
- Notes to Table 3–11: 52
- Atlantic Interface 54
- Note to Figure 3–17: 55
- Note to Table 3–13: 57
- Signal Naming Convention 58
- MegaCore Verification 59
- 1–2 Additional Information 62
- Typographic Conventions 62
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