Altera MAX 10 Clocking and PLL Manual do Utilizador Página 80
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Port Name Condition Description
read_param
Optional Reads the parameter specified with the counter_type and
counter_param ports from cache and fed to the data_
out[] port.
When asserted, the read_param signal indicates that the
scan cache should be read and fed to data_out[]. The bit
location of the scan cache and the number of bits read
and sent to data_out[] depend on the counter_type
and counter_param values. The read_param signal is
sampled at the rising clock edge. If the read_param signal
is asserted, the parameter value is read from the cache.
Assert the read_param signal for 1 clock cycle only to
prevent the parameter from being read twice.
The busy signal is asserted on the rising clock edge
following the assertion of the read_param signal. While
the parameter is read, the busy signal remains asserted.
After the busy signal is deasserted, the value on data_
out[] is valid and the next parameter can be loaded.
While the busy signal is asserted, the value on data_
out[] is not valid.
When the read_param signal is asserted, the busy signal is
only asserted on the following rising edge of the clock and
not on the same clock cycle as the read_param signal.
write_param
Optional Writes the parameter specified with the counter_type
and counter_param ports to the cache with the value
specified on the data_in[] port.
When asserted, the write_param signal indicates that the
value on data_in[] should be written to the parameter
specified by counter_type[] and counter_param[]. The
number of bits read from the data_in[] port depends on
the parameter. The write_param signal is sampled at the
rising clock edge. If the write_param signal is asserted,
the parameter value is written to the cache. Assert the
write_param signal for 1 clock cycle only to prevent the
parameter from being written twice.
The busy signal is asserted on the rising clock edge
following the assertion of the write_param signal. While
the parameter is being written, the busy signal remains
asserted and input to data_in[] is ignored. After the
busy signal is deasserted, the next parameter can be
written.
When the write_param signal is asserted, the busy signal
is only asserted on the following rising edge of the clock.
The busy signal is not asserted on the same clock cycle as
the write_param signal.
7-4
ALTPLL_RECONFIG Ports and Signals
UG-M10CLKPLL
2015.05.04
Altera Corporation
ALTPLL_RECONFIG IP Core References
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- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Contents 2
- Altera Corporation 3
- Clock Networks Overview 5
- Internal Oscillator Overview 5
- PLLs Overview 5
- • PLL cascading 6
- • Reference clock switchover 6
- Features 7
- Clock Resources 8
- Global Clock Network Sources 8
- Pin GCLK 9
- Global Clock Control Block 10
- Input Description 11
- Related Information 12
- Clock Enable Signals 13
- PLL Architecture 14
- UG-M10CLKPLL 15
- 2015.05.04 15
- PLL Features 16
- PLL Locations 16
- Clock Pin to PLL Connections 18
- PLL Control Signals 19
- Clock Feedback Modes 20
- Source Synchronous Mode 21
- No Compensation Mode 21
- Normal Mode 22
- PLL External Clock Output 23
- ADC Clock Input from PLL 25
- Spread-Spectrum Clocking 25
- PLL Programmable Parameters 25
- Programmable Phase Shift 26
- Clock Switchover 28
- Manual Clock Switchover 31
- PLL Cascading 32
- PLL Reconfiguration 32
- Considerations 35
- PLLs Design Considerations 36
- Guideline: PLL Cascading 37
- Guideline: Clock Switchover 37
- ALTCLKCTRL IP Core 39
- Search for installed IP cores 40
- ALTPLL IP Core 43
- Block Name 50
- Number of Bits 50
- Counter Control Bit Total 50
- 3. Ignore this directory 55
- ALTPLL_RECONFIG IP Core 56
- Internal Oscillator IP Core 59
- ALTCLKCTRL IP Core References 64
- ALTCLKCTRL Ports and Signals 65
- ALTPLL IP Core References 67
- Parameter Value Description 68
- ALTPLL Ports and Signals 72
- Port Name 73
- Condition Description 73
- ALTPLL_RECONFIG Parameters 77
- Parameter Value Decription 85
- Date Version Changes 86
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