Altera MAX 10 Clocking and PLL Manual do Utilizador Página 45
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Figure 4-4: Quartus II IP Catalog
Search for installed IP cores
Double-click to customize, right-click for
detailed information
Show IP only for target device
Note: The IP Catalog is also available in Qsys (View > IP Catalog). The Qsys IP Catalog includes
exclusive system interconnect, video and image processing, and other system-level IP that are not
available in the Quartus II IP Catalog. For more information about using the Qsys IP Catalog, refer
to Creating a System with Qsys in the Quartus II Handbook.
Specifying IP Core Parameters and Options
You can quickly configure a custom IP variation in the parameter editor. Use the following steps to
specify IP core options and parameters in the parameter editor. Refer to Specifying IP Core Parameters
and Options (Legacy Parameter Editors) for configuration of IP cores using the legacy parameter editor.
1. In the IP Catalog (Tools > IP Catalog), locate and double-click the name of the IP core to customize.
The parameter editor appears.
2. Specify a top-level name for your custom IP variation. The parameter editor saves the IP variation
settings in a file named <your_ip>.qsys. Click OK.
3. Specify the parameters and options for your IP variation in the parameter editor, including one or
more of the following. Refer to your IP core user guide for information about specific IP core
parameters.
UG-M10CLKPLL
2015.05.04
Specifying IP Core Parameters and Options
4-7
MAX 10 Clocking and PLL Implementation Guides
Altera Corporation
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- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Contents 2
- Altera Corporation 3
- Clock Networks Overview 5
- Internal Oscillator Overview 5
- PLLs Overview 5
- • PLL cascading 6
- • Reference clock switchover 6
- Features 7
- Clock Resources 8
- Global Clock Network Sources 8
- Pin GCLK 9
- Global Clock Control Block 10
- Input Description 11
- Related Information 12
- Clock Enable Signals 13
- PLL Architecture 14
- UG-M10CLKPLL 15
- 2015.05.04 15
- PLL Features 16
- PLL Locations 16
- Clock Pin to PLL Connections 18
- PLL Control Signals 19
- Clock Feedback Modes 20
- Source Synchronous Mode 21
- No Compensation Mode 21
- Normal Mode 22
- PLL External Clock Output 23
- ADC Clock Input from PLL 25
- Spread-Spectrum Clocking 25
- PLL Programmable Parameters 25
- Programmable Phase Shift 26
- Clock Switchover 28
- Manual Clock Switchover 31
- PLL Cascading 32
- PLL Reconfiguration 32
- Considerations 35
- PLLs Design Considerations 36
- Guideline: PLL Cascading 37
- Guideline: Clock Switchover 37
- ALTCLKCTRL IP Core 39
- Search for installed IP cores 40
- ALTPLL IP Core 43
- Block Name 50
- Number of Bits 50
- Counter Control Bit Total 50
- 3. Ignore this directory 55
- ALTPLL_RECONFIG IP Core 56
- Internal Oscillator IP Core 59
- ALTCLKCTRL IP Core References 64
- ALTCLKCTRL Ports and Signals 65
- ALTPLL IP Core References 67
- Parameter Value Description 68
- ALTPLL Ports and Signals 72
- Port Name 73
- Condition Description 73
- ALTPLL_RECONFIG Parameters 77
- Parameter Value Decription 85
- Date Version Changes 86
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