
B–4 Appendix B: Excluding Transceivers for Faster Simulation
External Transceiver Interface Clocks
Interlaken MegaCore Function June 2012 Altera Corporation
User Guide
Figure B–4 shows the clock diagram for an eight-lane variation that does not include
transceivers.
Figure B–4. Clock Diagram for 8-lane Interlaken MegaCore Function Without Transceivers
tx_lane_clk
tx_data[79:0]
rx_data[79:0]
rx_lane_clk[3:0]
rx_lane_clk[7:4]
tx_data[159:80]
tx_data[159:80]
common_rx_coreclk
Interlaken
MegaCore Function
tx_mac_clk
rx_mac_clk
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