Altera Interlaken MegaCore Function Manual do Utilizador Página 35
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Chapter 4: Functional Description 4–9
Clocking and Reset Structure
June 2012 Altera Corporation Interlaken MegaCore Function
User Guide
Figure 4–6 shows the clock diagram for a 20-lane Interlaken MegaCore function. This
variation uses the transceivers in PMA Direct mode. For more information, refer to
“High-Speed I/O Block” on page 4–22.
Interlaken MegaCore Function Recommended Clock Rates
This section describes the recommended frequencies for the Interlaken MegaCore
function clocks.
MAC Clock Verified Frequency
The Altera Interlaken MegaCore function supports the number of lanes and lane rate
combinations shown in Table 3–1 on page 3–2. The verified MAC clock rates for each
variation depend on the lane rate. Table 4–3 shows the MAC clock frequencies at
which the Interlaken MegaCore function was verified. The MAC clocks are the
tx_mac_c_cl
k and
rx_mac_c_clk
clocks.
Figure 4–6. Clock Diagram for 20-Lane Interlaken MegaCore Function
cal_blk_clk
ref_clk
clk_in
tx_datain[99:0]
clk_out (master TX clock)
common_rx_clk
rx_dataout[99:0]
rx_clk[4:0]
tx_lane_clk
tx_data[99:0]
rx_data[99:0]
rx_clk[4:0]
tx_data[199:100]
rx_data[199:100]
rx_clk[9:5]
tx_data[299:200]
common_rx_coreclk
rx_data[299:200]
rx_clk[14:10]
tx_data[399:300]
rx_data[399:300]
rx_clk[19:15]
HSIO Bank 0
(in PMA Direct mode)
cal_blk_clk
ref_clk
clk_in
tx_datain[99:0]
common_rx_clk
rx_dataout[99:0]
rx_clk[4:0]
HSIO Bank 1
(in PMA Direct mode)
HSIO Bank 2
(in PMA Direct mode)
HSIO Bank 3
(in PMA Direct mode)
tx_pin[4:0]
rx_pin[4:0]
tx_pin[4:0]
rx_pin[4:0]
cal_blk_clk
ref_clk
clk_in
tx_datain[99:0]
common_rx_clk
rx_dataout[99:0]
rx_clk[3:0]
tx_pin[4:0]
rx_pin[4:0]
cal_blk_clk
ref_clk
clk_in
Lanes 0 to 4
tx_datain[99:0]
common_rx_clk
rx_dataout[99:0]
rx_clk[4:0]
tx_pin[4:0]
rx_pin[4:0]
rx_c oreclkout
tx_coreclkout
x5
x5
x5
Lanes 5 to 9
Lanes 10 to 14
Lanes 15 to 19
x5
tx_mac_clk
rx_mac_clk
tx_mac_c_clk
rx_mac_c_clk
cal_blk_clk
ref_clk
TX MAC
and PCS
RX MAC
and PCS
Table 4–3. Verified MAC Block Frequencies in MHz (Part 1 of 2)
Number of Lanes
Lane Rate (Gbps)
3.125 6.25 6.375 10.3125
4 156.25 312.50 318.75 —
8 200.00 312.50 318.75 —
- User Guide 1
- Interlaken MegaCore Function 1
- Contents 3
- Chapter 5. Signals 4
- Contents v 5
- Features 7
- Device Family Support 8
- MegaCore Verification 9
- Release Information 10
- Installation and Licensing 10
- OpenCore Evaluation 12
- 2. Getting Started 13
- Qsys Design Flow Summary 14
- Qsys Design Flow 16
- Specifying Parameters 17
- Completing the Qsys System 18
- Simulating the System 18
- Specifying Constraints 19
- I/O Standard Constraints 20
- 3. Parameter Settings 23
- Lane Rate 24
- Number of Words in Meta Frame 24
- Exclude Transceiver 24
- Burst Parameters 25
- 4. Functional Description 27
- Architecture Overview 28
- Interfaces Overview 28
- Note to Table 4–1: 29
- Avalon-ST Interface 30
- Clocking and Reset Structure 31
- MAC Clock Verified Frequency 35
- PCS Clock Frequencies 36
- Transmit Path 37
- Receive Path 43
- Channel Filtering Blocks 45
- Packet Regrouper 45
- Calendar and Status Block 46
- Lane Status Block 47
- High-Speed I/O Block 48
- Transceivers 49
- 5. Signals 53
- Exclude transceivers 54
- Chapter 5: Signals 5–3 55
- Note to Table 5–2: 56
- Note to Table 5–3: 56
- Application Interface Signals 57
- Note to Table 5–6: 58
- Chapter 5: Signals 5–7 59
- Note to Table 5–8: 60
- Note to Table 5–9: 61
- Note to Table 5–10: 61
- Note to Table 5–11: 62
- Note to Table 5–12: 62
- Transceiver Banks 63
- Running a Design Example 65
- Setting Up the Design Example 66
- Function 69
- Simulation 73
- Reset Signals 79
- Required Reset Sequence 80
- Additional Information 87
- Typographic Conventions 88
- Visual Cue Meaning 89
- Info–4 Additional Information 90
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