Altera HardCopy II Clock Uncertainty Calculator Manual do Utilizador Página 28
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HardCopy II Clock Uncertainty Calculator User Guide
Various Clock Structures
Various Clock
Structures
When a clock is generated in the core, additional clock uncertainty may
be introduced by the additional routing. The HardCopy
®
II Clock
Uncertainty Calculator supports the following clock structures:
■ AND and MUX gated clocks
■ Clock divider
■ Ripple clock
■ Multiple clock networks
■ Multi-cycle clock
For each global and local clock network added to any of the examples in
Appendix A, clock uncertainty values should be increased by 25 ps. The
following examples are for intra-clock transfer with PLL; the same rules
apply for inter-clock transfer and I/O transfers, as well as for all cases not
involving PLLs.
Clock Gated in Core
In Figures 3–2 and 3–3, the source register is driven by an AND or MUX
gated clock, CLK2. Because the clock uncertainty calculator does not
account for the clock network on CLK2, you must add 25 ps on both the
setup and hold clock uncertainty values.
Figure 3–2. AND-Gated Clock for Intra-Clock Transfer
Figure 3–3. MUX-Gated Clock for Intra-Clock Transfer
PLL
INBUF
Source
Clock
Destination
Clock
Source
Register
Destinatio
n
Register
CLK1
CLK2
CLK3
PLL
INBUF
Source
Clock
Destination
Clock
Source
Register
Destinatio
n
Register
CLK1
CLK2
CLK3
- User Guide 1
- UG-01015-1.0 2
- Contents 3
- About this User Guide 5
- Typographic 6
- Conventions 6
- Chapter 1. About HardCopy II 7
- General 8
- Description 8
- PLL Extraction 9
- Clock Transfer Report 10
- Intra-Clock Transfer 11
- Inter-Clock Transfer 11
- I/O Transfer 12
- Instructions 12
- Clock Uncertainty Calculator 13
- 1–8 Altera Corporation 14
- General Description 14
- Chapter 2. Launching the 15
- HardCopy II Clock 15
- Uncertainty Calculator 15
- System and 16
- Software 16
- Requirements 16
- Running the 17
- Uncertainty 17
- Calculator Flow 17
- 2–4 Altera Corporation 18
- Altera Corporation 2–5 19
- 2–6 Altera Corporation 20
- Altera Corporation 2–7 21
- 2–8 Altera Corporation 22
- Altera Corporation 2–9 23
- 2–10 Altera Corporation 24
- Altera Corporation 2–11 25
- 2–12 Altera Corporation 26
- Chapter 3. Design Case 27
- Exceptions 27
- Various Clock 28
- Structures 28
- Clock Divider 29
- Ripple Clock 29
- Multiple Clock Networks 30
- Multi-Cycle Clock 30
- Altera Corporation 3–5 31
- Design Case Exceptions 31
- Clock Transfer Type 32
- Setup CU (ps) Hold CU (ps) 32
- Intra-Clock 32
- Inter-Clock 32
- I/O Interface 32
- Appendix A. Clock Transfer 33
- Examples 33
- A–2 Altera Corporation 34
- Intra-Clock Domain with PLL 34
- 11 — 11 — 34
- Domain without 35
- Domain with 36
- Altera Corporation A–5 37
- A–6 Altera Corporation 38
- Inter-Clock Domain with PLL 38
- Altera Corporation A–7 39
- A–8 Altera Corporation 40
- 12 — 0 — 40
- Altera Corporation A–9 41
- Altera Corporation A–13 45
- Cascaded PLLs 46
- Altera Corporation A–15 47
- Altera Corporation A–17 49
- A–18 Altera Corporation 50
- Altera Corporation A–19 51
- A–20 Altera Corporation 52
- Altera Corporation A–21 53
- A–22 Altera Corporation 54
- 12 3 12 7 54
- Altera Corporation A–23 55
- A–24 Altera Corporation 56
- 0 — 10 11 56
- Altera Corporation A–25 57
- 12 2 0 — 57
- A–26 Altera Corporation 58
- 10 — 4 8 58
- Altera Corporation A–27 59
- A–28 Altera Corporation 60
- A–30 Altera Corporation 62
- 10 2 0 — 62
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