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November 2013 Altera Corporation Cyclone V SoC Development Kit
User Guide
A. Programming Flash Memory
This appendix describes programming information for the following memory
devices:
■ Common flash interface (CFI) flash memory
■ Quad serial peripheral interface (quad SPI) flash memory
■ SD card flash memory
The Cyclone V development board’s flash memory ships preconfigured with the
parallel flash loader (PFL) option bits to support FPGA designs to be written to any of
the three locations as shown in Table A–1. The PFL is disabled by default. Set SW2.3 to
ON to enable FPGA programming from CFI flash memory on power up.
1 There are several other factory software files written to flash memory to support the
Board Update Portal. These software files were created using the Nios II EDS, just as
the hardware design was created using the Quartus II software.
CFI Flash Memory
CFI Flash Memory Map
Table A–1 shows the default memory contents of the 512 Mb CFI flash device.
c Altera recommends that you do not overwrite the factory hardware images unless
you are an expert with Altera tools. If you unintentionally overwrite the factory
hardware or factory software image, refer to “Restoring the CFI Flash Device to the
Factory Defaults” on page 3–6.
Programming CFI Flash Using the Quartus II Programmer
You can use the JTAG interface in Altera CPLDs to indirectly program the flash
memory device. The Altera CPLD JTAG block interfaces directly with the logic array
in a special JTAG mode. This mode brings the JTAG chain through the logic array
instead of the Altera CPLD boundary-scan cells (BSC). The PFL megafunction
provides JTAG interface logic to do the following:
■ Convert the JTAG stream provided by the Quartus II software.
Table A–1. Byte Address Flash Memory Map
Block Description KB Size Address Range
Unused 44711 0x0145.635C - 03FF.FFFF
User hardware 2 6872 0x00DA.0000 - 0145.635B
User hardware 1 6872 0x006E.0000 - 00D9.635B
Factory hardware 6872 0x0002.0000 - 006D.635B
PFL option bits 32 0x0001.8000 - 0001.8080
- User Guide 1
- Cyclone V SoC Development Kit 1
- Contents 3
- Additional Information 4
- 1. About This Kit 5
- References 6
- 2. Software Installation 7
- <install dir> 8
- <version> 8
- 3. Development Board Setup 11
- Note to Table 3–4: 15
- 4. Board Update Portal 17
- 5. Board Test System 19
- Running the Board Test System 20
- Board Information 21
- JTAG Chain 22
- Character LCD 23
- User DIP Switch 23
- User LEDs 24
- Push Button Switches 24
- Using the Board Test System 25
- Performance Indicators 26
- Error Control 27
- The SDI Video Tab 28
- Pattern Generator 29
- Start, Stop 31
- XCVR, LVDS, CMOS 32
- The Power Monitor 33
- U34 and U26 34
- Controls 34
- The Clock Control 35
- Serial Port Registers 36
- Target Frequency 36
- Set New Frequency 37
- A. Programming Flash Memory 39
- CFI Flash Memory 40
- SD Card Memory 42
- Info–2 Additional Information 44
- Typographic Conventions 44
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