Altera Cyclone V GT FPGA Development Board Manual do Utilizador descarregar pdf (Página 48)

2–40 Chapter 2: Board Components

Memory

Cyclone V GT FPGA Development Board September 2014 Altera Corporation

Reference Manual

DDR3A_DQ19

AJ21 1.5-V SSTL Class I Data bus byte lane 2

DDR3A_DQ20

AH21 1.5-V SSTL Class I Data bus byte lane 2

DDR3A_DQ21

AH22 1.5-V SSTL Class I Data bus byte lane 2

DDR3A_DQ22

AP30 1.5-V SSTL Class I Data bus byte lane 2

DDR3A_DQ23

AN28 1.5-V SSTL Class I Data bus byte lane 2

DDR3A_DQ24

AL23 1.5-V SSTL Class I Data bus byte lane 3

DDR3A_DQ25

AK23 1.5-V SSTL Class I Data bus byte lane 3

DDR3A_DQ26

AL25 1.5-V SSTL Class I Data bus byte lane 3

DDR3A_DQ27

AM26 1.5-V SSTL Class I Data bus byte lane 3

DDR3A_DQ28

AK24 1.5-V SSTL Class I Data bus byte lane 3

DDR3A_DQ29

AJ24 1.5-V SSTL Class I Data bus byte lane 3

DDR3A_DQ30

AN31 1.5-V SSTL Class I Data bus byte lane 3

DDR3A_DQ31

AL28 1.5-V SSTL Class I Data bus byte lane 3

DDR3A_DQS_P2

AJ20

Differential 1.5-V SSTL

Class I

Data strobe P byte lane 2

DDR3A_DQS_N2

AK20

Differential 1.5-V SSTL

Class I

Data strobe N byte lane 2

DDR3A_DQS_P3

Y20

Differential 1.5-V SSTL

Class I

Data strobe P byte lane 3

DDR3A_DQS_N3

AA20

Differential 1.5-V SSTL

Class I

Data strobe N byte lane 3

DDR3A_ODT

AN21 1.5-V SSTL Class I On-die termination enable

DDR3A_RASN

AP14 1.5-V SSTL Class I Row address select

DDR3A_RESETN

AJ22 1.5-V SSTL Class I Reset

DDR3A_WEN

AN12 1.5-V SSTL Class I Write enable

DDR3A_ZQ2

— 1.5-V SSTL Class I ZQ impedance calibration

DDR3 x16 (U28)

DDR3A_A0

AK18 1.5-V SSTL Class I Address bus

DDR3A_A1

AL18 1.5-V SSTL Class I Address bus

DDR3A_A2

AM18 1.5-V SSTL Class I Address bus

DDR3A_A3

AN18 1.5-V SSTL Class I Address bus

DDR3A_A4

AH17 1.5-V SSTL Class I Address bus

DDR3A_A5

AJ17 1.5-V SSTL Class I Address bus

DDR3A_A6

AK17 1.5-V SSTL Class I Address bus

DDR3A_A7

AL17 1.5-V SSTL Class I Address bus

DDR3A_A8

AH16 1.5-V SSTL Class I Address bus

DDR3A_A9

AJ16 1.5-V SSTL Class I Address bus

DDR3A_A10

AL16 1.5-V SSTL Class I Address bus

DDR3A_A11

AM16 1.5-V SSTL Class I Address bus

Table 2–28. DDR3A Device Pin Assignments, Schematic Signal Names, and Functions (Part 4 of 5)

Board Reference

Schematic

Signal Name

Cyclone V GT

Pin Number

I/O Standard Description

1 2 ... 43 44 45 46 47 48 49 50 51 52 53 ... 65 66

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