Altera Cyclone V GT FPGA Development Board Manual do Utilizador descarregar pdf (Página 47)

Chapter 2: Board Components 2–39

Memory

September 2014 Altera Corporation Cyclone V GT FPGA Development Board

Reference Manual

DDR3A_DQS_P1

AD19

Differential 1.5-V SSTL

Class I

Data strobe P byte lane 1

DDR3A_DQS_N1

AE19

Differential 1.5-V SSTL

Class I

Data strobe N byte lane 1

DDR3A_ODT

AN21 1.5-V SSTL Class I On-die termination enable

DDR3A_RASN

AP14 1.5-V SSTL Class I Row address select

DDR3A_RESETN

AJ22 1.5-V SSTL Class I Reset

DDR3A_WEN

AN12 1.5-V SSTL Class I Write enable

DDR3A_ZQ01

— 1.5-V SSTL Class I ZQ impedance calibration

DDR3 x16 (U27)

DDR3A_A0

AK18 1.5-V SSTL Class I Address bus

DDR3A_A1

AL18 1.5-V SSTL Class I Address bus

DDR3A_A2

AM18 1.5-V SSTL Class I Address bus

DDR3A_A3

AN18 1.5-V SSTL Class I Address bus

DDR3A_A4

AH17 1.5-V SSTL Class I Address bus

DDR3A_A5

AJ17 1.5-V SSTL Class I Address bus

DDR3A_A6

AK17 1.5-V SSTL Class I Address bus

DDR3A_A7

AL17 1.5-V SSTL Class I Address bus

DDR3A_A8

AH16 1.5-V SSTL Class I Address bus

DDR3A_A9

AJ16 1.5-V SSTL Class I Address bus

DDR3A_A10

AL16 1.5-V SSTL Class I Address bus

DDR3A_A11

AM16 1.5-V SSTL Class I Address bus

DDR3A_A12

AM13 1.5-V SSTL Class I Address bus

DDR3A_A13

AN13 1.5-V SSTL Class I Address bus

DDR3A_BA0

AN16 1.5-V SSTL Class I Bank address bus

DDR3A_BA1

AN17 1.5-V SSTL Class I Bank address bus

DDR3A_BA2

AP17 1.5-V SSTL Class I Bank address bus

DDR3A_CASN

AP15 1.5-V SSTL Class I Row address select

DDR3A_CKE

AP26 1.5-V SSTL Class I Column address select

DDR3A_CLK_P

AA18

Differential 1.5-V SSTL

Class I

Differential output clock

DDR3A_CLK_N

AA17

Differential 1.5-V SSTL

Class I

Differential output clock

DDR3A_CSN

AA16 1.5-V SSTL Class I Chip select

DDR3A_DM2

AM28 1.5-V SSTL Class I Write mask byte lane

DDR3A_DM3

AL27 1.5-V SSTL Class I Write mask byte lane

DDR3A_DQ16

AP27 1.5-V SSTL Class I Data bus byte lane 2

DDR3A_DQ17

AN27 1.5-V SSTL Class I Data bus byte lane 2

DDR3A_DQ18

AK22 1.5-V SSTL Class I Data bus byte lane 2

Table 2–28. DDR3A Device Pin Assignments, Schematic Signal Names, and Functions (Part 3 of 5)

Board Reference

Schematic

Signal Name

Cyclone V GT

Pin Number

I/O Standard Description

1 2 ... 42 43 44 45 46 47 48 49 50 51 52 ... 65 66

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