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2–12 Chapter 2: Board Components
Configuration, Status, and Setup Elements
Cyclone IV GX Transceiver Starter Board Reference Manual © March 2010 Altera Corporation
FPGA Configuration using External USB-Blaster
The JTAG programming header provides another method for configuring the FPGA
using an external USB-Blaster device with the Quartus II Programmer running on a
PC. The external USB-Blaster is connected to the board through the JTAG connector
(J1).
Figure 2–4 on page 2–10 illustrates the JTAG chain.
By default, the FPGA is the first device in the JTAG chain. To add the MAX II CPLD
EPM2210 System Controller into the JTAG chain, set the board settings DIP switch
(S8.3) to '0'. When the starter board is plugged into a PCI Express slot, you can add the
PCI Express card into the JTAG chain by setting the board settings DIP switch (S8.4) to
'1'.
Table 2–11 on page 2–14 summarizes the board settings DIP switch controls.
FPGA Configuration using EPCS Device
Active serial configuration can be performed using an Altera
®
EPCS device. During
configuration, the FPGA is the master and the EPCS128 device is the slave. The
configuration data is transferred to the FPGA on the DATA0 pin at a rate of one bit per
clock cycle. This configuration data is synchronized to the DCLK input.
1 Before you program the EPCS device, set the configuration DIP switch (S7) to select
the AS configuration scheme as shown in Table 2–13 on page 2–14. After
programming the EPCS device, the design is loaded from the EPCS device to the
FPGA when you power up the board.
EPCS Programming
EPCS programming is possible through a variety of methods. One method to program
the EPCS device is to use the Serial FlashLoader (SFL), a JTAG-based in-system
programming solution for Altera serial configuration devices. The SFL is a bridge
design for the FPGA that uses the JTAG connector (J1) to access the JTAG Indirect
Configuration Device Programming File (.jic) and then uses the AS interface to
program the EPCS device. Both the JTAG and AS interfaces are bridged together
inside the SFL design.
Another method to program the EPCS device is to perform in-system programming
through the AS programming header (J12).
Other methods to program the EPCS can be used as well, including the Nios II
processor.
f For more information on the following topics, refer to the respective documents:
Topic Reference
Board Update Portal Cyclone IV GX Transceiver Starter Kit User Guide
PFL Design Cyclone IV GX Transceiver Starter Kit User Guide
PFL Megafunction AN 386: Using the Parallel Flash Loader with the Quartus II Software
SFL Megafunction AN 370: Using the Serial FlashLoader with the Quartus II Software
Managing and programming
EPCS memory contents
Nios II Flash Programmer User Guide
- Reference Manual 1
- MNL-01053-1.0 2
- Contents 3
- 1. Overview 5
- Board Component Blocks 6
- Chapter 1: Overview 1–3 7
- Starter Board Block Diagram 8
- Handling the Board 8
- 2. Board Components 9
- Board Overview 10
- I/O Resources 13
- Table 2–6 lists the MAX 16
- Configuration 17
- Note to Table 2–8: 19
- Status Elements 21
- Setup Elements 21
- Note to Table 2–11: 22
- Notes to Table 2–13: 23
- Clock Circuitry 24
- User-Defined LEDs 25
- General User Input/Output 26
- PCI Express 27
- 10/100/1000 Ethernet 29
- Power Distribution System 34
- Power Supply 35
- Power Measurement 36
- Notes to Table 2–35: 37
- Note to Table: 39
- Typographic Conventions 40
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