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A–2 Appendix A: Constraints

Constraint Design With TimeQuest Timing Analyzer

Asynchronous Serial Interface (ASI) MegaCore Function User Guide January 2014 Altera Corporation

The following constraints demonstrate how to properly constrain the ASI

MegaCore RX and TX targeting Stratix IV devices.

Specify Clock Characteristics

Use the following constraints for the TimeQuest timing analyzer:

■ ASI RX (Hard Transceiver) (

rx_clk135

= 135 MHz)

create_clock -name {rx_clk135} -period 7.407 -waveform { 0.000 3.703 }

[get_ports {rx_clk135}]

■ ASI TX (Hard Transceiver) (

tx_clk135

= 135 MHz,

tx_refclk

= 27 MHz)

create_clock -name {tx_clk135} -period 7.407 -waveform { 0.000 3.703 }

[get_ports {tx_clk135}]

create_clock -name {tx_refclk} -period 37.037 -waveform { 0.000 18.518 }

[get_ports {tx_refclk}]

■ ASI RX (Soft Transceiver) (

rx_clk135

= 135 MHz,

rx_serial_clk

= 337.5 MHz,

rx_serial_clk90

= 337.5 MHz)

create_clock -name {rx_clk135} -period 7.407 -waveform { 0.000 3.703 }

[get_ports {rx_clk135}]

create_clock -name {rx_serial_clk} -period 2.963 -waveform { 0.000 1.481

} [get_ports {rx_serial_clk}]

create_clock -name {rx_serial_clk90} -period 2.963 -waveform { 0.000

1.481 } [get_ports {rx_serial_clk90}]

■ ASI TX (Soft Transceiver) (

tx_clk270

= 270 MHz,

tx_refclk

= 27 MHz)

create_clock -name {tx_clk270} -period 3.704 -waveform { 0.000 1.852 }

[get_ports {tx_clk270}]

create_clock -name {tx_refclk} -period 37.037 -waveform { 0.000 18.518

} [get_ports {tx_refclk}]

1 To avoid the

u_rx_pll|c0

and

u_rx_pll|c2

nodes from getting synthesized away

during analysis and synthesis, make sure the reset port of the core is connected to an

input pin and not to the ground; and apply the following additional constraints on the

two nodes:

set_instance_assignment -name IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL ON -to

"u_rx_pll|c0"

set_instance_assignment -name IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL ON -to

"u_rx_pll|c2"

Define the Setup and Hold Relationship between the 135-MHz Clocks and the

337.5-MHz zero-degree Clocks

■ ASI TX (Soft Transceiver)

Use the following commands to specify an absolute minimum and maximum delay

for a given path.

set_min_delay -from [get_clocks {tx_refclk}] -to [get_clocks

{tx_clk270}] 0.000

set_max_delay -from [get_clocks {tx_refclk}] -to [get_clocks

{tx_clk270}] 33.333

1 2 ... 18 19 20 21 22 23 24 25 26 27

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