Altera Arria V SoC Manual do Utilizador descarregar pdf (Página 24)

5–4 Chapter 5: Board Test System

Using the Board Test System

Arria V SoC Development Kit June 2014 Altera Corporation

User Guide

Board Information

The Board information controls display static information about your board.

■ Board Name—Indicates the official name of the board.

■ Part number—Indicates the part number of the board.

■ Serial number—Indicates the serial number of the board.

■ Factory test version—Indicates the version of the Board Test System currently

running on the board.

■ MAC1—Indicates the MAC address of the board's ENET1 10/100 port.

■ MAC2—Indicates the MAC address of the board's ENET2 10/100 port.

■ HPS MAC1—Indicates the MAC address of the board's HPS 10/100/1000

Ethernet port.

■ MAX V ver—Indicates the version of MAX V code currently running on the

board. The MAX V code resides in the <install

dir>\kits\arriaVST_5astfd5kf40es_soc\examples directory. Newer revisions of

this code might be available on the Arria V SoC Development Kit page of the

Altera website.

JTAG Chain

The JTAG chain control shows all the devices currently in the JTAG chain. The

Arria V device is always the first device in the chain. The JTAG chain is normally

mastered by the On-board USB-Blaster II.

1 If you plug in an external USB-Blaster cable to the JTAG header (J35), the On-Board

USB-Blaster II is disabled.

1 JTAG DIP switch bank (SW4) selects which interfaces are in the chain. Refer to

Table 3–3 on page 3–4 for detailed settings.

f For details on the JTAG chain, refer to the Arria V SoC Development Board Reference

Manual. For USB-Blaster II configuration details, refer to the On-Board USB-Blaster II

page.

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Altera Arria V SoC Manual do Utilizador Página 24